DS1497 datasheet(7/19 Pages) DALLAS

7 / 19 page

DS1495/DS1497

020894 7/19

TIME, CALENDAR AND ALARM DATA MODES Table 1

ADDRESS

FUNCTION

DECIMAL

RANGE

ADDRESS

LOCATION

FUNCTION

DECIMAL

RANGE

BINARY DATA MODE

BCD DATA MODE

Seconds

0-59

00-3B

00-59

Seconds Alarm

0-59

00-3B

00-59

Minutes

0-59

00-3B

00-59

Minutes Alarm

0-59

00-3B

00-59

Hours-12-hr Mode

1-12

01-0C AM, 81-8C PM

01-12AM,81-92PM

Hours-24-hr Mode

0-23

00-17

00-23

Hours Alarm-12-hr

1-12

01-0C AM, 81-8C PM

01-12AM,81-92PM

Hours Alarm-24-hr

0-23

00-17

00-23

Day of the Week

Sunday = 1

1-7

01-07

Date of the Month

1-31

01-1F

01-31

Month

1-12

01-0C

01-12

Year

0-99

00-63

00-99

INTERRUPTS

The RTC plus RAM includes three separate, fully auto-

matic sources of interrupt for a processor. The alarm in-

terrupt can be programmed to occur at rates from once

per second to once per day. The periodic interrupt can

be selected for rates from 500 ms to 122

µs. The up-

date-ended interrupt can be used to indicate to the pro-

gram that an update cycle is complete. Each of these

independent interrupt conditions is described in greater

detail in other sections of this text.

The application program can select which interrupts, if

any, are going to be used. Three bits in Register B en-

able the interrupts. Writing a logic 1 to an interrupt-en-

able bit permits that interrupt to be initiated when the

event occurs. A logic 0 in an interrupt-enable bit prohib-

its the IRQ pin from being asserted from that interrupt

condition. If an interrupt flag is already set when an in-

terrupt is enabled, IRQ is immediately set at an active

level, although the interrupt initiating the event may

have occurred much earlier. As a result, there are cases

where the program should clear such earlier initiated in-

terrupts before first enabling new interrupts.

When an interrupt event occurs, the relating flag bit is

set to logic 1 in Register C. These flag bits are set inde-

pendent of the state of the corresponding enable bit in

without enabling the corresponding enable bits. When a

flag is set, an indication is given to software that an inter-

rupt event has occurred since the flag bit was last read.

However, care should be taken when using the flag bits

as they are cleared each time Register C is read.

Double latching is included with Register C so that bits

which are set remain stable throughout the read cycle.

All bits which are set (high) are cleared when read and

new interrupts which are pending during the read cycle

are held until after the cycle is completed. One, two, or

three bits can be set when reading Register C. Each uti-

lized flag bit should be examined when read to ensure

that no interrupts are lost.

The alternative flag bit usage method is with fully en-

abled interrupts. When an interrupt flag bit is set and the

corresponding interrupt enable bit is also set, the IRQ

pin is asserted low. IRQ is asserted as long as at least

one of the three interrupt sources has its flag and enable

bits both set. The IRQF bit in Register C is a one when-

ever the IRQ pin is being driven low. Determination that

the RTC initiated an interrupt is accomplished by read-

ing Register C. A logic one in bit 7 (IRQF bit) indicates

that one or more interrupts have been initiated by the

DS1495/DS1497. The act of reading Register C clears

all active flag bits and the IRQF bit.

DS1497 Datasheet(PDF) 7 Page - Dallas Semiconductor

DS1497 Datasheet(HTML) 7 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

Datasheet Download

Link URL