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DS1667 Datasheet(PDF) 2 Page - Dallas Semiconductor |
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DS1667 Datasheet(HTML) 2 Page - Dallas Semiconductor |
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2 / 10 page ![]() DS1667 2 of 10 same. The DS1667 also contains two high gain wide bandwidth operational amplifiers. Each amplifier has both the inverting and non-inverting inputs and the output available for user configuration. The operational amplifiers can be paired with the resistive elements to perform such functions as analog to digital conversion, digital to analog conversion, variable gain amplifiers, and variable oscillators. OPERATION - DIGITAL RESISTOR SECTION The DS1667 contains two potentiometers, each of which has its wiper set by a value contained in an 8-bit register (see Figure 1). Each potentiometer consists of 256 resistors of equal value with tap points between each resistor and at the low end. In addition, the potentiometer can be stacked by connecting them in series such that the high end of potentiometer 0 is connected to the low end of potentiometer 1. When stacking potentiometers, the stack select bit is used to select which potentiometer wiper will appear at the stack multiplexer output (SOUT). A zero written to the stack multiplexer will connect wiper 0 to the SOUT pin. This wiper will determine which of the 256 bottom taps of the stacked potentiometer is selected. When a 1 is written to the stack multiplexer, wiper 1 is selected and one of the upper 256 taps of the stacked potentiometer is presented at the SOUT pin. BLOCK DIAGRAM Figure 1 Information is written to and read from the wiper 0 and wiper 1 registers and the stack select bit via the 17-bit I/O shift register. The I/O shift register is serially loaded by a 3-wire serial port consisting of RST , DQ, and CLK. It is updated by transferring all 17 bits (Figure 2). Data can be entered into the 17-bit shift register only when the RST input is at a high level. While at a high level, the RST function allows serial entry of data via the D/Q pin. The potentiometers always maintain their previous value until RST is taken to a low level, which terminates data transfer. While RST input is low, the DQ and CLK inputs are ignored. |
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