ICS571

LOW PHASE NOISE ZERO DELAY BUFFER

ZDB AND MULTIPLIER/DIVIDER

IDT™ / ICS™ LOW PHASE NOISE ZERO DELAY BUFFER

5

ICS571

REV H 051310

AC Electrical Characteristics

Unless stated otherwise, VDD = 5.0 V or 3.3 V, Ambient Temperature 0 to +70

° C

Notes:

1. Sresses beyond these can permanently damage the device.

2. Assumes clocks with the same rise time, measured from rising edges at VDD/2. Measured with 33

Ω termination

resistors and 15 pF loads. Applies to both 3.3 V and 5 V operation.

3. CLK/2 has lower jitter (both absolute and one sigma, in ps) than CLK.

Thermal Characteristics

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency, clock input

FB from CLK

20

160

MHz

Input Frequency, clock input

FB from CLK/2

10

80

MHz

Skew CLK/2 with respect to CLK

Note 2

150

500

850

ps

Input clock to output connected to FBIN

Note 2

-500

500

ps

Output Clock Rise Time, 5 V

0.8 to 2.0 V, 15 pF load

0.3

ns

Output Clock Fall Time, 5 V

2.0 to 0.8 V, 15 pF load

0.4

ns

Output Clock Rise Time, 3.3 V

0.8 to 2.0 V, 15 pF load

0.45

ns

Output Clock Fall Time, 3.3 V

2.0 to 0.8 V, 15 pF load

0.55

ns

Input Clock Duty Cycle, 3.3 V

fin = 150 MHz

20

80

%

Output Clock Duty Cycle, 3.3 V

At VDD/2

45

49 to 51

55

%

Absolute Clock Period Jitter, CLK,

Note 3

Deviation from Mean

±80

ps

One-Sigma Clock Period Jitter, CLK,

Note 3

50

ps

Phase Noise, Relative to carrier

1 kHz offset

-105

dBc/Hz

Phase Noise, Relative to carrier

100 kHz offset

-115

dBc/Hz

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Thermal Resistance Junction to

Ambient

Still air

° C/W

1 m/s air flow

° C/W

3 m/s air flow

° C/W

Thermal Resistance Junction to Case

° C/W