DS1807 datasheet(12/13 Pages) DALLAS

12 / 13 page

DS1807

12 of 13

110499

NOTES:

1. All voltages are referenced to ground.

2. I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VDD is switched off.

3. ICC specified with zero-crossing detection active and operating device serial port in fast mode.

4. ISTBY specified with for VCC equal 3.0V and 5.0V and SDA and SCL are driven to the appropriate

logic levels. ISTBY is specified as the current consumption of the device when SDA and SCL are in the

inactive (high) states.

5. After this period, the first clock pulse is generated.

6. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the

VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.

7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the

SCL signal.

8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT > 250 ns must

then be met. This will automatically be the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next

data bit to the SDA line tRMAX + tSU:DAT = 1000+250=1250 ns before the SCL line is released.

9. CB - total capacitance of one bus line in picofarads, timing referenced to (0.9(VCC) and (0.1)(VCC)).

10. Absolute tolerance is used to determine measured wiper voltage versus expected wiper voltage as

determined by wiper position.

11. Tap-to-tap tolerance is used to determine the change in voltage between successive tap positions. The

DS1807 is specified for a

±0.25 dB tap-to-tap tolerance.

12. Typical values are for tA = 25

°C and nominal supply voltage.

13. Address inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired

address selections.

14. These parameters are characterized and not 100% tested.

15. Interchannel matching is used to determine the relative difference in dB between the same position on

each potentiometer. The DS1807 is specified for

±0.5 dB Interchannel matching

16. See Figure 9.

17. Valid at 25

°C only.

DS1807 Datasheet(PDF) 12 Page - Dallas Semiconductor