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DS1821 Datasheet(PDF) 10 Page - Dallas Semiconductor

Part # DS1821
Description  Programmable Digital Thermostat
PDF  16 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1821 Datasheet(HTML) 10 Page - Dallas Semiconductor

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DS1821
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READ/WRITE TIME SLOTS
DS1821 data is read and written through the use of time slots to manipulate bits and a command word to
specify the transaction.
Write Time Slots
A write time slot is initiated when the host pulls the data line from a high logic level to a low logic level.
There are two types of write time slots: Write 1 time slots and Write 0 time slots. All write time slots
must be a minimum of 60
µs in duration with a minimum of a 1-µs recovery time between individual
write cycles.
The DS1821 samples the DQ line in a window of 15
µs to 60 µs after the DQ line falls. If the line is high,
a Write 1 occurs. If the line is low, a Write 0 occurs (see Figure 6).
For the host to generate a Write 1 time slot, the data line must be pulled to a logic low level and then
released, allowing the data line to pull up to a high level within 15 microseconds after the start of the
write time slot.
For the host to generate a Write 0 time slot, the data line must be pulled to a logic low level and remain
low for the duration of the write time slot.
Read Time Slots
The host generates read time slots when data is to be read from the DS1821. A read time slot is initiated
when the host pulls the data line from a logic high level to logic low level. The data line must remain at a
low logic level for a minimum of 1 µs; output data from the DS1821 is then valid for the next 14 µs
maximum. The host therefore must stop driving the DQ pin low in order to read its state 15 µs from the
start of the read slot (see Figure 6). By the end of the read time slot, the DQ pin will pull back high via the
external pullup resistor. All read time slots must be a minimum of 60 µs in duration with a minimum of a
one µs recovery time between individual read slots.
Figure 7 shows that the sum of TINIT, TRC, and TSAMPLE must be less than 15 µs. Figure 8 shows that
system timing margin is maximized by keeping TINIT and TRC as small as possible and by locating the
master sample time towards the end of the 15-µs period.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 5



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