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DS2172T Datasheet(PDF) 7 Page - Dallas Semiconductor |
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DS2172T Datasheet(HTML) 7 Page - Dallas Semiconductor |
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7 / 21 page ![]() DS2172 7 of 21 PLR: PATTERN LENGTH REGISTER (Address=04 Hex) (MSB) (LSB) - - - LB4 LB3 LB2 LB1 LB0 SYMBOL POSITION NAME AND DESCRIPTION - PLR1.7 Not Assigned. Should be set to 0 when written to. - PLR1.6 Not Assigned. Should be set to 0 when written to. - PLR1.5 Not Assigned. Should be set to 0 when written to. LB4 PLR1.4 Length Bit 4. LB3 PLR1.3 Length Bit 3. LB2 PLR1.2 Length Bit 2. LB1 PLR1.1 Length Bit 1. LB0 PLR1.0 Length Bit 0. 5.0 POLYNOMIAL TAP REGISTER Polynomial Tap Bits PT4 - PT0 determine the feedback position of Tap B connected to the XOR input of the pattern generator. Feedback Tap B provides one of two feedback paths within the pattern generator. Please refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for register programming examples. PTR: POLYNOMIAL TAP REGISTER (Address=05 Hex) (MSB) (LSB) - - - PT4 PT3 PT2 PT1 PT0 SYMBOL POSITION NAME AND DESCRIPTION -PTR.7 Not Assigned. Should be set to 0 when written to. -PTR.6 Not Assigned. Should be set to 0 when written to. -PTR.5 Not Assigned. Should be set to 0 when written to. PT4 PTR.4 Polynomial Tap Bit 4. PT3 PTR.3 Polynomial Tap Bit 3. PT2 PTR.2 Polynomial Tap Bit 2. PT1 PTR.1 Polynomial Tap Bit 1. PT0 PTR.0 Polynomial Tap Bit 0. |
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