DS2433

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64-BIT LASERED ROM

Each DS2433 contains a unique ROM code that is 64 bits long. The first eight bits are a 1-Wire family

code. The next 48 bits are a unique serial number. The last eight bits are a CRC of the first 56 bits. (See

Figure 3.) The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and

XOR gates as shown in Figure 4. The polynomial is X

Dallas 1-Wire Cyclic Redundancy Check is available in the Book of DS19xx iButton Standards.

The shift register bits are initialized to zero. Then starting with the least significant bit of the family code,

one bit at a time is shifted in. After the 8

is entered. After the 48

value. Shifting in the eight bits of CRC should return the shift register to all zeros.

MEMORY

The memory map in Figure 5 shows a 32-byte page called the scratchpad and additional 32-byte pages

called memory. The DS2433 contains pages 0 through 15 which make up the 4096-bit EEPROM. The

scratch-pad is an additional page that acts as a buffer when writing to memory.

ADDRESS REGISTERS AND TRANSFER STATUS

Because of the serial data transfer, the DS2433 employs three address registers, called TA1, TA2 and E/S

(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be

written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte

counter and Transfer Status register. It is used to verify data integrity with write commands. Therefore,

the master only has read access to this register. The lower five bits of the E/S register indicate the address

of the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the

E/S register, called PF, is set if the number of data bits sent by the master is not an integer multiple of 8 or

if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad will clear

the PF bit. Bit 6 has no function; it always reads 0. Note that the lowest five bits of the target address

also determine the address within the scratchpad, where intermediate storage of data will begin. This

address is called byte offset. If the target address (TA1) for a Write command is 03CH for example, then

the scratchpad will store incoming data beginning at the byte offset 1CH and will be full after only four

bytes.

The corresponding ending offset in this example is 1FH.

For best economy of speed and

efficiency, the target address for writing should point to the beginning of a new page, i.e., the byte offset

will be 0. Thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset

of 1FH. However, it is possible to write one or several contiguous bytes somewhere within a page. The

ending offset together with the Partial Flag support the master checking the data integrity after a Write

command. The highest valued bit of the E/S register, called AA is valid only if the PF flag reads 0. If PF

is 0 and AA is 1, a copy has taken place. The AA bit is cleared when the device receives a write

scratchpad command.

WRITING WITH VERIFICATION

To write data to the DS2433, the scratchpad has to be used as intermediate storage. First the master

issues the Write Scratchpad command to specify the desired target address, followed by the data to be

written to the scratchpad. Under certain conditions (see Write Scratchpad command) the master will

receive an inverted CRC16 of the command, address and data at the end of the write scratchpad command

sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to

decide if the communication was successful and proceed to the Copy Scratchpad command. If the master

could not receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to

verify data integrity. As preamble to the scratchpad data, the DS2433 repeats the target address TA1 and

TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the