DS80CH11 datasheet(21/88 Pages) DALLAS

21 / 88 page

DS80CH11

011200 21/88

INSTRUCTION SET SUMMARY Table 3–1 (cont’d)

Bit Manipulation

Instructions:

CLR C

ANL C, bit

CLR bit

ANL C, bit

SETB C

ORL C, bit

SETB bit

ORL C, bit

CPL C

MOV C, bit

CPL bit

MOV bit, C

Program Branching

Instructions:

ACALL addr 11

CJNE A, direct, rel

LCALL addr 16

CJNE A, #data, rel

RET

CJNE Rn, #data, rel

RETI

CJNE @ Ri, #data, rel

AJMP addr 11

NOP

LJMP addr 16

JC rel

SJMP rel

JNC rel

JMP @A+DPTR

JB bit, rel

JZ rel

JNB bit, rel

JNZ rel

JBC bit, rel

DJNZ Rn, rel

DJNZ direct, rel

The Table above shows the speed for each class of

instruction. Note that many of the instructions have mul-

tiple opcodes. There are 255 opcodes for 111 instruc-

tions. Of the 255 opcodes, 159 are three times faster

than the original 80C32. While a system than empha-

sizes those instructions will see the most improvement,

the large total number that receive a three to one

improvement assure a dramatic speed increase for any

system. The speed improvement summary is provided

below.

3.3

SPEED IMPROVEMENT

The following table summarizes the speed improve-

ment of the High Speed Micro core over a standard 12

clock / machine cycle 8052 device.

#Opcodes

Speed Improvement

159

3.0 x

1.5 x

2.0 x

2.4 x

255

Average: 2.5

3.4

INSTRUCTION SET ADDITIONAL

REFERENCES

The user should refer to the Dallas High Speed Micro

User’s Guide for a complete description of the instruc-

tion set including its address modes, coding, and timing

for the SEM.

3.5

RESET

The High–Speed Micro has three ways of entering a

reset state:

• Power–On / Fail Reset

• Watchdog Timer Reset

• External Reset

The operation of the CPU timing and states during a

reset are documented in the Dallas High Speed Micro

User’s Guide under the “Reset Conditions” section. The

Watchdog Timer reset is documented in the Watchdog

Timer section of the Dallas High Speed Micro User’s

Guide. The operation of the Power–On / Fail reset is

described in the Power Management section of this doc-

ument.

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