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LTC6946 Datasheet(PDF) 12 Page - Linear Technology

Part # LTC6946
Description  Ultralow Noise and Spurious 0.37GHz to 5.7GHz Integer-N Synthesizer with Integrated VCO
PDF  30 Pages
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Manufacturer  LINER [Linear Technology]
Direct Link  http://www.linear.com
Logo LINER - Linear Technology

LTC6946 Datasheet(HTML) 12 Page - Linear Technology

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LTC6946
12
6946fa
BLOCK DIAGRAM
RF–
28
2
3
11
GND
10
MUTE
9
RF+
12
VRF
+
13
27
REF–
REFO
≤250MHz
≤100MHz
÷1 TO 1023
÷1 TO 6, 50%
÷32 TO 65535
0.373GHz TO
5.79GHz
MUTE
1
VREFO
+
REF+
26
VREF
+
R_DIV
LOCK
PFD
O_DIV
N_DIV
B_DIV
CAL, ALC
CONTROL
2.24GHz TO 3.74GHz (LTC6946-1) OR
3.08GHz TO 4.91GHz (LTC6946-2) OR
3.84GHz TO 5.79GHz (LTC6946-3)
TUNE
15
CP
VVCO
+
GND
CMA
CMB
CMC
GND
250μA TO
11.2mA
25
22
21
20
19
18
17
24
VCP
+
23
GND
16
TB
6946 BD
14
BB
SERIAL
PORT
STAT
CS
7
SDO
SDI
SCLK
8
VD
+
6
5
4
OPERATION
The LTC6946 is a high performance PLL complete with
a low noise VCO available in three different frequency
range options. The output frequency range may be further
extended by utilizing the output divider (see Available Op-
tions table, for more details). The device is able to achieve
superior integrated phase noise by the combination of
its extremely low in-band phase noise performance and
excellent VCO noise characteristics.
REFERENCE INPUT BUFFER
The PLL’s reference frequency is applied differentially on
pins REF+ and REF–. These high impedance inputs are
self-biased and must be AC-coupled with 470pF capacitors
(see Figure 1 for a simplified schematic). Alternatively, the
inputs may be used single ended by applying the refer-
ence frequency at REF+ and bypassing REF– to GND with
a 470pF capacitor.
A high quality signal must be applied to the REF± inputs as
they provide the frequency reference to the entire PLL. To
achieve the part’s in-band phase noise performance, apply
27
28
4.2k
REF+
REF–
4.2k
6946 F01
1.9V
BST
BIAS
VREF
+
VREF
+
LOWPASS
FILT[1:0]
Figure 1. Simplified REF Interface Schematic
a CW signal of at least 6dBm into 50Ω, or a square wave
of at least 0.5VP-P with slew rate of at least 40V/μs.
Additional options are available through serial port register
h08 to further refine the application. Bits FILT[1:0] control
the reference input buffer’s lowpass filter, and should be
set based upon fREF to limit the reference’s wideband
noise. The FILT[1:0] bits must be set correctly to reach
the LM(NORM) normalized in-band phase noise floor. See
Table 1 for recommended settings.



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