Product Specification

SP4272

Page 2 of 10

Table 2. Pin Descriptions

Table 4. Absolute Maximum Ratings

Electrostatic Discharge (ESD) Precautions

When handling this CMOS device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the rating specified in Table 4.

Latch-Up Avoidance

Unlike conventional CMOS devices, CMOS

devices are immune to latch-up.

Table 3. Operating Ranges

Note:

4. All RF pins must be DC blocked with an external

Figure 3. Pin Configuration (Top View)

4272

1

2

3

4

8

7

6

5

V

DD

CTRL

GND

RFC

RF1

GND

GND

RF2

Pin

No.

Pin

Name

Description

1

Nominal +3 V supply connection.

2

CTRL

CMOS logic level:

High = RFC to RF1 signal path

Low = RFC to RF2 signal path

3

GND

Ground connection. Traces should be

physically short and connected to ground

plane for best performance.

4

RFC

5

RF2

6

GND

Ground Connection. Traces should be

physically short and connected to ground

plane for best performance.

7

GND

Ground Connection. Traces should be

physically short and connected to ground

plane for best performance.

8

RF1

Symbol

Parameter/Conditions

Min

Max

Units

Power supply voltage

-0.3

4.0

V

Voltage on any input

-0.3

0.3

V

Storage temperature range

-65

150

°C

P

IN

Input power (50

Ω)

34

dBm

ESD voltage (HBM, ML_STD

883 Method 3015.7)

1500

V

Parameter

Min

Typ

Max

Units

2.7

3.0

3.3

V

8

20

µA

Control Voltage High

V

Control Voltage Low

V

Operating temperature

range

-40

85

°C

Absolute Maximum Ratings are those values

listed in the above table. Exceeding these values

may cause permanent device damage.

Functional operation should be restricted to the

limits in the Operating Ranges table. Exposure to

absolute maximum ratings for extended periods

may affect device reliability.

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