Product Specification

SP4273

Page 2 of 10

Table 2. Pin Descriptions

Table 3. Absolute Maximum Ratings

Electrostatic Discharge (ESD) Precautions

When handling this CMOS device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the rating specified in Table 3.

Latch-Up Avoidance

Unlike conventional CMOS devices, CMOS

devices are immune to latch-up.

Table 4. DC Electrical Specifications

Figure 3. Pin Configuration (Top View)

1

2

3

4

5

6

V2

RFC

V1

RF1

GND

RF2

pin 1

Pin

No.

Pin

Name

Description

1

RF1

RF Port1

4

2

GND

Ground connection. Traces should be

physically short and connected to ground

plane for best performance.

3

RF2

RF Port2

4

4

V1

Switch control input, CMOS logic level.

5

RFC

RF Common

4

6

V2

This pin supports two interface options:

Single-pin control mode. A nominal 3-

volt supply connection is required.

Complementary-pin control mode. A

complementary CMOS control signal

to V1 is supplied to this pin.

Symbol

Parameter/Conditions

Min

Max

Units

Power supply voltage

-0.3

4.0

V

Voltage on any input

-0.3

0.3

V

Storage temperature

range

-65

150

°C

Operating temperature

range

-40

85

°C

Input power (50

Ω)

+34

dBm

ESD Voltage (HBM,

ML_STD 883 Method

3015.7)

1500

V

ESD Voltage (MM,

JEDEC, JESD22-A114-B)

100

V

Parameter

Min

Typ

Max

Units

Voltage

2.7

3.0

3.3

V

(V1 = 3V, V2= 3V)

8

50

µA

Control Voltage High

V

Control Voltage Low

V

Note: 4. All RF pins must be DC blocked with an external series

capacitor or held at 0 VDC.

Absolute Maximum Ratings are those values

listed in the above table. Exceeding these values

may cause permanent device damage.

Functional operation should be restricted to the

limits in the DC Electrical Specifications table.

Exposure to absolute maximum ratings for

extended periods may affect device reliability.

Note: 5. Operating within DC limits (Table 4).

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