Product Specification

SP4302

Page 8 of 10

Table 7. 6-Bit Attenuator Serial Programming

Register Map

Table 9. Parallel Interface AC Characteristics

Figure 18. Parallel Interface Timing Diagram

Table 8. Serial Interface AC Characteristics

Figure 17. Serial Interface Timing Diagram

LE

Clock

Data

MSB

LSB

t

LESUP

t

SDSUP

t

SDHLD

t

LEPW

B5

B4

B3

B2

B1

B0

C16

C8C4

C2C1

C0.5

↑↑

LSB (last in)

MSB (first in)

t

PDSUP

t

PDHLD

Parallel Data

C16:C0.5

LE

t

LEPW

Symbol

Parameter

Min

Max

Unit

Serial data clock

frequency (Note 1)

10

MHz

Serial clock HIGH time

30

ns

Serial clock LOW time

30

ns

LE set-up time after last

clock falling edge

10

ns

LE minimum pulse width

30

ns

Serial data set-up time

before clock rising edge

10

ns

Serial data hold time

after clock falling edge

10

ns

programming sections of the functional pattern are clocked at

10 MHz to verify fclk specification.

Symbol

Parameter

Min

Max

Unit

LE minimum pulse width

10

ns

Data set-up time before

rising edge of LE

10

ns

Data hold time after

falling edge of LE

10

ns

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