Product Specification

SP43701

Page 9 of 12

Table 12. Parallel and Direct Interface AC

Table 11. Serial Interface AC Characteristics

Note:

programming sections of the functional pattern are clocked

at 10 MHz to verify fclk specification.

Figure 20. Serial-Addressable Timing Diagram

Figure 21. Latched-Parallel/Direct-Parallel Timing Diagram

Symbol

Parameter

Min

Max

Unit

Serial clock frequency

-

10

MHz

Serial clock HIGH time

30

-

ns

Serial clock LOW time

30

-

ns

Last serial clock rising edge

setup time to Latch Enable

rising edge

10

-

ns

Latch Enable min. pulse width

30

-

ns

Serial data setup time

10

-

ns

Serial data hold time

10

-

ns

Parallel data setup time

100

-

ns

Parallel data hold time

100

-

ns

Address setup time

100

-

ns

Address hold time

100

-

ns

Parallel/Serial setup time

100

-

ns

Parallel/Serial hold time

100

-

ns

Digital register delay (internal)

-

10

ns

Symbol

Parameter

Min

Max

Unit

Latch Enable minimum

pulse width

30

-

ns

Parallel data setup time

100

-

ns

Parallel data hold time

100

-

ns

Parallel/Serial setup time

100

-

ns

Parallel/Serial hold time

100

-

ns

Digital register delay

(internal)

-

10

ns

Digital register delay

(internal, direct mode only)

-

5

ns

Characteristics

VALID

T

DISU

T

DIH

DI[6:0]

LE

P/S

T

PSSU

T

PSH

T

LEPW

VALID

DO[6:0]

T

DIPD

T

PD

Bits can either be set to logic high or logic low

A[2]

A[1]

A[0]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

T

SISU

T

CLKL

T

LEPW

T

SIH

T

CLKH

SI

CLK

LE

P/S

T

LESU

T

PSSU

T

PSH

VALID

T

ASU

ADD[2:0]

T

AH

DO[6:0]

VALID

DI[6:0]

T

PD

T

DISU

T

DIH

D[0]

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