CM-2 datasheet(18/54 Pages) CIRRUS

18 / 54 page

DS651UM23

Version 2.3

CobraNet Hardware User’s Manual

Synchronization

The following synchronization modes are further described below:

• "Internal Mode" on page 18

• "External Word Clock Mode" on page 18

• "External Master Clock Mode" on page 18

5.1.1 Internal Mode

All CobraNet clocks are derived from the onboard VCXO. The master clock generated by

the VCXO is available to external circuits via the master clock output.

Conductor—The VCXO is “parked” according to the

syncClockTrim setting.

Performer—The VCXO is “steered” to match the clock transmitted by the Conductor.

5.1.2 External Word Clock Mode

All CobraNet clocks are derived from the onboard VCXO. The VCXO is steered from an

external clock supplied to the reference clock input. The clock supplied can be any

integral division of the sample clock in the range of 750Hz to 48kHz.

External synchronization lock range: ±5

µs. This specification indicates drift or wander

between the supplied clock and the generated network clock at the conductor. Absolute

phase difference between the supplied reference clock and generated sample clock is

dependant on network topology.

Conductor—This mode gives a means for synchronizing an entire CobraNet network to

an external clock.

Performer—The interface disregards the fine timing information delivered over the

network from the conductor. Coarse timing information from the conductor is still used;

fine timing information is instead supplied by the reference clock. The external clock

source must be synchronous with the network conductor. This mode is useful in

installations where a house sync source is readily available.

5.1.3 External Master Clock Mode

The VCXO is disabled and MCLK_IN is used as the master clock for the node. This is a

“hard” synchronization mode. The supplied clock is used directly by the CobraNet

interface for all timing. This mode is primarily useful for devices with multiple CobraNet

interfaces sharing a common master audio clock. The supplied clock must be

24.576 MHz. The supplied clock must have a ±37 ppm precision.

Conductor—The entire network is synchronized to the supplied master clock.

Performer—The node will initially lock to the network clock and will “jam sync” via the

supplied master clock. The external clock source must be synchronous with the network

conductor.

CM-2 Datasheet(PDF) 18 Page - Cirrus Logic