App Note

July 2004

A subsidiary of TT electronics plc

PRINCIPLE OF OPERATION

Basically, all a successful PFC design has to do is force the input current to follow the input line voltage regardless of

what the load current (the switching power supply) is doing. If the input current is sinusoidal then the harmonic and

peak current problems are solved, and if the input current is in phase with the input voltage a unity power factor will

be achieved. Note that the line voltage is tacitly assumed to remain sinusoidal. This will only be true if the source

impedance of the power line is sufficiently low. Active PFCs can achieve .999 power factors with less than 3% total

harmonic distortion.

While there are other topologies, the most common boost type will be discussed here. At first glance, the circuit

appears to be just a step up boost voltage regulator. While indeed regulating its output voltage, an active PFC also

modulates the current through the inductor to force the input current to be sinusoidal. It accomplishes this by using the

input voltage as a sinewave current reference signal.

This reference is compared to the actual input current

(determined by a current sense resistor or transformer) in order to generate an error signal. This error signal is

‘processed and combined’ with the output voltage error signal and a voltage feed forward signal to form the control

input to a pulse width modulator (PWM). The PWM then drives the active switch, usually a power FET or IGBT, thus

closing the control loop in order to create the desired sinusoidal input current.

There are really two control loops, voltage and current, plus an open loop voltage feed forward signal. The trick to an

effective design rests with properly compensating these control loops, and the feed forward signal. The design details

are best left to the application note for the specific control IC being employed, but the basic idea is that the current

control loop must respond fast enough to modify the current into a sinusoid during the input cycle of 60 Hz.

Typically, bandwidth is around 10kHz for a 100 kHz switching frequency.

However, the voltage control bandwidth must be low otherwise output regulation would be so rapid within a power

line cycle that the input current would be completely distorted. Consequently, the voltage loop bandwidth is set to

several power line cycles, around 20 Hz. That is, the slower the voltage loop response the lower the input current

distortion, but the poorer the output voltage transient response becomes. Thus, for a given distortion the output

capacitor must be increased in value until a satisfactory output voltage transient response is obtained.

To understand the ‘processing and combining’ of signals by the control IC, think in terms of power control, not

voltage or current. Properly functioning, a PFC’s instantaneous real input to real output power must remain constant

(unity at 100% efficiency) despite variations in input voltage. For example, if the input voltage doubles the current

must be halved if the power is to remain the same. The control IC accomplishes this by taking the input voltage and

dividing by the feed forward voltage squared. The feed forward voltage is just the average (filtered) input voltage.

Therefore, twice the input voltage divided by four times the input (feed forward voltage squared) results in one half the

constant during a single line cycle. This is a reasonable assumption since the voltage loop responds slowly (20 Hz).