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EL4581CS Datasheet(PDF) 3 Page - Elantec Semiconductor |
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EL4581CS Datasheet(HTML) 3 Page - Elantec Semiconductor |
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3 / 12 page ![]() EL4581C Sync Separator 50% Slice S-H Filter Dynamic Characteristics VDD e 5V IV pk-pk video TA e 25 C CL e 15 pF IOH eb16 mA IOL e 16 mA Signal voltages are peak to peak Parameter Description Temp Min Typ Max Test Units Level Vertical Sync Width tVS (Note 3) 25 C 190 230 300 I ms BurstBack Porch Width tB (Note 3) 25 C 25 35 45 I ms Vertical Sync Default Delay tVSD 25 C40 55 70 I ms Filter Attenuation FIN e 34 MHz (Note 4) 25 C24 V dB Composite Sync Prop Delay VINb Composite Sync 25 C 260 400 I ns (Note 3) Input Dynamic Range p-p NTSC Signal 25 C 05 2 I V (Note 5) Slice Level Input Voltage e 1VP-P 25 C 40% 50% 60% I (Note 6) Full 40% 50% 60% IV Note 3 CS Vertical and Burst outputs are all active low b VOH e 24V VOL e 08V Note 4 Attenuation is a function of Rset (PIN6) Note 5 Typical min is 03 VP-P Note 6 Refers to threshold level of sync tip to back porch amplitude Pin Descriptions Pin No Pin Name Function 1 Composite Sync Out Composite sync pulse output Sync pulses start on a falling edge and end on a rising edge 2 Composite Video in AC coupled composite video input Sync tip must be at the lowest potential (Positive picture phase) 3 Vertical Sync Out Vertical sync pulse output The falling edge of Vert Sync is the start of the vertical period 4 GND Supply ground 5 BurstBack Porch Output BurstBack porch output Low during burst portion of composite video 6RSET An external resistor to ground sets all internal timing 681k 1% resistor will provide correct timing for NTSC signals 7 OddEven Output OddEven field output Low during odd fields high during even fields Transitions occur at start of Vert Sync pulse 8VDD 5V Positive supply (5V) Note RSET must be a 1% resistor 3 |
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