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80960JF Datasheet(PDF) 17 Page - Intel Corporation |
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80960JF Datasheet(HTML) 17 Page - Intel Corporation |
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17 / 86 page ![]() 80960JA/JF/JD/JS/JC/JT 3.3 V Embedded 32-Bit Microprocessor Datasheet 17 Table 7. Pin Description Nomenclature Symbol Description I Input pin only. O Output pin only. I/O Pin may be either an input or output. – Pin must be connected as described. S Synchronous. Inputs must meet setup and hold times relative to CLKIN for proper operation. S(E) Edge sensitive input S(L) Level sensitive input A (...) Asynchronous. Inputs may be asynchronous relative to CLKIN. A(E) Edge sensitive input A(L) Level sensitive input R (...) While the processor’s RESET# pin is asserted, the pin: R(1) is driven to VCC R(0) is driven to VSS R(Q) is a valid output R(X) is driven to unknown state R(H) is pulled up to VCC H (...) While the processor is in the hold state, the pin: H(1) is driven to VCC H(0) is driven to VSS H(Q) Maintains previous state or continues to be a valid output H(Z) Floats P (...) While the processor is halted, the pin: P(1) is driven to VCC P(0) is driven to VSS P(Q) Maintains previous state or continues to be a valid output |
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