* This specification are subject to be changed without notice.

EM19100

8-BIT 20 MSPS VIDEO A/D CONVERTER (CMOS)

4

1.26.1996

Timing explanation

EM19100 is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group and 2 lower

comparators groups of 4-bit each. The reference voltage that is equal to the voltage between V

constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the upper data is fed through

the reference supply to the lower data. V

voltage top) and V

This IC uses an offset cancel type comparator and operates synchronously with an external clock. It features the

following operating modes which are respectively indicated on the timing chart with S, H, C symbols. That is

input sampling (auto zero) mode, input hold mode and comparison mode.

The operation of respective parts is as indicated in the chart. For instance input voltage Vi(1) is sampled with the

falling edge of the first clock by means of the upper comparator block and the lower comparator A block. The

upper comparators block finalizes comparison data MD(1) with the rising edge of the first clock. Simultaneously

the reference supply generates the lower reference voltage RV(1) that corresponded to the upper results. The

lower comparator block finalizes comparison data LD(1) with the rising edge of the second clock. MD(1) and

LD(1) are combined and output as Out(1) with the rising edge the 3rd clock. Accordingly there is a 2.5 clock delay

from the analog input sampling point to the digital data output.

Application Note

V

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital and

analog V

respective GND’s.

Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small. However

it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. When

driving with an amplifier of low output impedance, parasite oscillation may occur. That may be prevented by

inserting a resistance of about 100

Ω in series between the amplifier output and A/D input.

Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals, separate

it from other circuits

Reference input

Voltage between V

V

and V

Timing

Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks and