3

* This specification are subject to be changed without notice.

EM92600/1A

DUAL PLL FOR 46/49 MHZ CORDLESS PHONE

4.23.1995

Symbol

I/O

Function

D0

I

The channel selected pin. LSB.(intenal pull down)

D1

I

The channel selected pin. (internal pull down)

D2

I

The channel selected pin. (internal pull down)

D3

I

The channel selected pin. MSB.(internal pull down)

Di

I

The serial input data pin.

CLK

I

Clock input. Each low to high transition of the clock shifts one bit of data into

the on-chip shift register.

NC

-

Not connect.

EN

I

The enable pin controls the data transfer from the shift register to the 4-bit latch.

A low to high transition latches the data.

TIF

I

Input to programmable divider of Tx. AC coupling with VCO. Min input voltage

is 200mVpp.

LD

O

Unlock detector output. V

PDT

O

Phase detector output for Tx. PDT detects the phase error from Tx PLL and its

output is connected to external low pass filter.

V

SS

-

Ground.

PDR

O

Phase detector output for Rx. PDR detects the phase error from Rx PLL and its

output is connected to external low pass filter.

RIF

I

Input of programmable divider for Rx.AC coupling with VCO. Min input voltage

is 200mVpp.

V

DD

-

Power supply.

XTAL1

I

To connect crystal ( 10.240MHz ) and capacitor.

ABSOLUTE MAXIMUM RATINGS

Symbol

Rating

Value

Unit

V

DD

DC supply voltage

-0.5 to +6

V

V

IN

Input voltage

-0.5 to V

V

I

IN

,I

OUT

DC current drain per pin

10.0

mA

I

DC current drain V

30.0

mA

T

A

Operating temperature range

-30 to +75

°C

T

STG

Storage temperature range

-65 to +150

°C