ZXFV4583

SEMICO NDUC TORS

ISSUE 3 - NOVEMBER 2003

4

PIN No.

PIN NAME

TYPE

FUNCTION

1

Resistor

control

Controls the input color carrier filter characteristic. An external

description below.

2

Resistor

control

connected from this pin to 0V sets the threshold voltage level,

according to the equation

3

CSYNC

Logic out

Composite sync logic output. Includes all sync pulses derived from

the input video.

4

FILTIN

Analog in

Input to color carrier filter. This is the main analog (unfiltered)

composite video input used when color carrier filtering is required. A

voltage clamp circuit and adaptive current source are also included

at this node. See the detailed operating description. When the filter

is not used, this pin must be left open circuit.

5

VSYNC

Logic out

Vertical sync output. This is an active low pulse commencing on the

first vertical sync pulse trailing (rising) edge and ending near the

second next equalizing pulse. See timing diagram.

6

OVD

Ground

Provides ground return path for internal logic output buffer circuits.

Normally connected externally to a common PCB ground plane.

7

FILTOUT

Analog out Analog output signal from color carrier filter. The filter voltage gain

is nominally 2. This output is normally capacitor-coupled to pin 8.

8

FVIDIN

Analog in

Input for filtered analog video signal input. This is the direct input

to the sample/hold and sync slicing comparator providing the logic

timing edges. This input is normally coupled via an external

capacitor from FILTOUT, pin 7. It may be used as the signal input

where the color carrier filter is not required. Includes a clamp

similar that of pin 4.

9

VLEV

Analog out Analog output, a positive voltage typically equal to twice the

(negative) peak sync pulse amplitude if the filter is used.

10

NOSIG

Logic out

Logic output, which goes high after a time-out delay when no signal

is present. The threshold level is controlled at pin 2.

11

BKPCH

Logic out

Burst or Back Porch logic output, an active low monostable pulse

triggered from rising composite sync pulse edges. The width is set

assuming the color carrier burst has been attenuated sufficiently by

filtering. This pulse is then suitable for controlling an external black

level clamping circuit. See the timing diagram.

12

Resistor

control

Controls the timing interval of the sample/hold circuit and the

monostable interval for the sync outputs according to the

establishes the timing parameter, to which these times are scaled

together. See the detailed operating description.

13

ODDFLD

Logic out

Odd field logic output. High during an odd numbered field, low

during even. This output is timed with the start of the VSYNC pulse.

14

V+

Power in

Power supply input, +5V.

15

HSYNC

Logic out

Horizontal sync logic output. Monostable output derived from

CSYNC falling edges, it achieves a steady stream of 5µs pulses. The

half line events during the field blanking interval are eliminated. See

timing diagram.

CONNECTIONS