LM3100MH datasheet(13/21 Pages) TI1

13 / 21 page

tSS =

8 PA

CSS x 0.8V

CIN =

IOUT x tON

LM3100

www.ti.com

SNVS421F – JANUARY 2006 – REVISED DECEMBER 2009

At maximum load current, when the buck switch turns on, the current into VIN suddenly increases to the lower

peak of the inductor’s ripple current, ramps up to the peak value, then drop to zero at turn-off. The average

current during the on-time is the load current. For a worst case calculation, CIN must supply this average load

current during the maximum on-time. CIN is calculated from:

(12)

where IOUT is the load current, tON is the maximum on-time, and ΔV is the allowable ripple voltage at VIN.

CIN3’s purpose is to help avoid transients and ringing due to long lead inductance at VIN. A low ESR, 0.1µF

ceramic chip capacitor is recommended, located close to the LM3100.

CBST: The recommended value for CBST is 33 nF. A high quality ceramic capacitor with low ESR is recommended

as CBST supplies a surge current to charge the buck switch gate at turn-on. A low ESR also helps ensure a

complete recharge during each off-time.

CSS: The capacitor at the SS pin determines the soft-start time, i.e. the time for the reference voltage at the

regulation comparator, and the output voltage, to reach their final value. The time is determined from the

following:

(13)

CFB: If output voltage is higher than 1.6V, this feedback capacitor is needed for Discontinuous Conduction Mode

to improve the output ripple performance, the recommended value for CFB is 10 nF.

PC BOARD LAYOUT

The LM3100 regulation, over-voltage, and current limit comparators are very fast, and will respond to short

duration noise pulses. Layout considerations are therefore critical for optimum performance. The layout must be

as neat and compact as possible, and all external components must be as close as possible to their associated

pins. Refer to the functional block diagram, the loop formed by CIN, the high and low-side switches internal to the

IC, and the PGND pin should be as small as possible. The PGND connection to Cin should be as short and

direct as possible. There should be several vias connecting the Cin ground terminal to the ground plane placed

as close to the capacitor as possible. The boost capacitor should be connected as close to the SW and BST pins

as possible. The feedback divider resistors and the CFB capacitor should be located close to the FB pin. A long

trace run from the top of the divider to the output is generally acceptable since this is a low impedance node.

Ground the bottom of the divider directly to the GND (pin 7). The output capacitor, COUT, should be connected

close to the load and tied directly into the ground plane. The inductor should connect close to the SW pin with as

short a trace as possible to help reduce the potential for EMI (electro-magnetic interference) generation.

If it is expected that the internal dissipation of the LM3100 will produce excessive junction temperatures during

normal operation, good use of the PC board’s ground plane can help considerably to dissipate heat. The

exposed pad on the bottom of the IC package can be soldered to a ground plane and that plane should extend

out from beneath the IC to help dissipate the heat. The exposed pad is internally connected to the IC substrate.

Additionally the use of thick copper traces, where possible, can help conduct heat away from the IC. Using

numerous vias to connect the die attach pad to an internal ground plane is a good practice. Judicious positioning

of the PC board within the end product, along with the use of any available air flow (forced or natural convection)

can help reduce the junction temperature.

Submit Documentation Feedback

Product Folder Links: LM3100

LM3100MH Datasheet(PDF) 13 Page - Texas Instruments

LM3100MH Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21

Datasheet Download

Link URL