LM3475 datasheet(12/21 Pages) TI1

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LM3475

SNVS239A – OCTOBER 2004 – REVISED JANUARY 2005

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DIODE SELECTION

The catch diode provides the current path to the load during the PFET off time. Therefore, the current rating of

the diode must be higher than the average current through the diode, which be calculated as shown:

ID_AVE = IOUT x (1 − D)

(11)

The peak voltage across the catch diode is approximately equal to the input voltage. Therefore, the diode’s peak

reverse voltage rating should be greater than 1.3 times the input voltage.

A Schottky diode is recommended, since a low forward voltage drop will improve efficiency.

For high temperature applications, diode leakage current may become significant and require a higher reverse

voltage rating to achieve acceptable performance.

P-CHANNEL MOSFET SELECTION

The PFET switch should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating

(ID), maximum Gate-Source voltage (VGS), on resistance (RDSON), and Gate capacitance. The voltage across the

PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must

be selected to provide some margin beyond the sum of the input voltage and Vd.

Since the current flowing through the PFET is equal to the current through the inductor, ID must be rated higher

than the maximum IPK. During switching, PGATE swings the PFET’s gate from VIN to ground. Therefore, A PFET

must be selected with a maximum VGS larger than VIN. To insure that the PFET turns on completely and quickly,

refer to the PGATE section.

The power loss in the PFET consists of switching losses and conducting losses. Although switching losses are

difficult to precisely calculate, the equation below can be used to estimate total power dissipation. Increasing

RDSON will increase power losses and degrade efficiency. Note that switching losses will also increase with lower

gate threshold voltages.

PDswitch = RDSONx (IOUT)

2x D + F x I

OUTx VINx (ton + toff)/2

where

•

ton = FET turn on time

•

toff = FET turn off time

•

A value of 10ns to 50ns is typical for ton and toff

(12)

Note that the RDSON has a positive temperature coefficient. At 100°C, the RDSON may be as much as 150% higher

than the value at 25°C.

The Gate capacitance of the PFET has a direct impact on both PFET transition time and the power dissipation in

the LM3475. Most of the power dissipated in the LM3475 is used to drive the PFET switch. This power can be

calculated as follows:

The amount of average gate driver current required during switching (IG) is:

IG = Qg x F

(13)

And the total power dissipated in the device is:

IqVIN + IGVIN

where

•

Iq is typically 260µA as shown in Electrical Characteristics

(14)

As gate capacitance increases, operating frequency may need to be reduced, or additional heat sinking may be

required to lower the power dissipation in the device.

In general, keeping the gate capacitance below 2000pF is recommended to keep transition times (switching

losses), and power losses low.

REDUCING SWITCHING NOISE

Although the LM3475 employs internal noise suppression circuitry, external noise may continue to be excessive.

There are several methods available to reduce noise and EMI.

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