LM5022MM datasheet(21/34 Pages) TI1

21 / 34 page

100

10k

100k

FREQUENCY (Hz)

-30

-15

Qn =

-D + 0.5 + (1 - D)

LM5022

www.ti.com

SNVS480E – JANUARY 2007 – REVISED OCTOBER 2011

(49)

The sampling double corner frequency is:

ωn = π x fSW

(50)

The natural inductor current slope is:

Sn = RSNS x VIN / L

(51)

The external ramp slope is:

Se = 45 µA x (2000 + RS1 + RS2)] x fSW

(52)

In the equation for APS, DC gain is highest when input voltage and output current are at the maximum. In this the

example those conditions are VIN = 16V and IO = 500 mA.

DC gain is 44 dB. The low frequency pole fP = 2πωP is at 423Hz, the ESR zero fZ = 2πωZ is at 5.6 MHz, and the

right-half plane zero fRHP = 2πωRHP is at 61 kHz. The sampling double-pole occurs at one-half of the switching

frequency. Proper selection of slope compensation (via RS2) is most evident the sampling double pole. A well-

selected RS2 value eliminates peaking in the gain and reduces the rate of change of the phase lag. Gain and

phase plots for the power stage are shown in Figure 9.

Figure 9. Power Stage Gain and Phase

Submit Documentation Feedback

Product Folder Links: LM5022

LM5022MM Datasheet(PDF) 21 Page - Texas Instruments