TLV705 datasheet(11/24 Pages) TI1

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TLV705

TLV705P

www.ti.com

SBVS151C – DECEMBER 2010 – REVISED OCTOBER 2012

APPLICATION INFORMATION

The TLV705 and TLV705P series of devices belong

BOARD LAYOUT RECOMMENDATIONS TO

to a new family of next-generation value low-dropout

IMPROVE PSRR AND NOISE PERFORMANCE

(LDO)

voltage

regulators.

They

consume

low

Input and output capacitors should be placed as

quiescent current and deliver excellent line and load

close to the device pins as possible. To improve ac

transient performance. This performance, combined

performance (such as PSRR, output noise, and

with low noise, very good PSRR with little (VIN –

transient response), it is recommended that the board

VOUT) headroom, makes these devices ideal for RF

be designed with separate ground planes for VIN and

portable applications. This family of regulators offers

VOUT, with the ground plane connected only at the

sub-bandgap output voltages down to 0.7 V, current

GND pin of the device. In addition, the ground

limit, and thermal protection, and are specified from

connection

for

the

output

capacitor

should

–40°C to +125°C. The TLV705P provides an active

connected directly to the GND pin of the device. High

pull-down circuit to quickly discharge the outputs.

ESR capacitors may degrade PSRR.

INPUT AND OUTPUT CAPACITOR

INTERNAL CURRENT LIMIT

REQUIREMENTS

The internal current limits of the TLV705 series help

μF X5R- and X7R-type ceramic capacitors are

protect the regulator during fault conditions. During

recommended

because

these

components

have

current limit, the output sources a fixed amount of

minimal variation in value and equivalent series

current that is largely independent of output voltage.

resistance (ESR) over temperature. However, the

In such a case, the output voltage is not regulated,

TLV705 series is designed to be stable with an

and can be measured as VOUT = ILIMIT × RLOAD. The

effective capacitance of 0.1

μF or larger at the output.

PMOS pass transistor dissipates [(VIN – VOUT) × ILIMIT]

Thus, the device would also be stable with capacitors

until a thermal shutdown is triggered and the device

other

dielectrics

long

the

effective

turns off. As the device cools down, it is turned on by

capacitance under the operating bias voltage and

the internal thermal shutdown circuit. If the fault

temperature is greater than 0.1

μF. This effective

condition continues, the device cycles between

capacitance refers to the capacitance that the LDO

current limit and thermal shutdown; see the Thermal

sees under operating bias voltage and temperature

Information section for more details.

conditions (that is, the capacitance after taking the

bias

voltage

and

temperature

derating

into

The PMOS pass element in the TLV705 has a built-in

consideration). In addition to allowing the use of lower

body diode that conducts current when the voltage at

cost dielectrics, it also enables using smaller footprint

VOUT exceeds the voltage at VIN. This current is not

capacitors that have higher derating in space-

limited, so if extended reverse voltage operation is

constrained applications.

anticipated, external limiting to 5% of rated output

current is recommended.

Note that using a 0.1-

μF rating capacitor at the output

of the LDO does not ensure stability because the

SOFT-START

effective capacitance under operating conditions

would be less than 0.1

μF. Maximum ESR should be

The startup current is given by Equation 1. This

less than 200 m

Ω.

equation shows that soft-start current is directly

proportional to COUT.

Although an input capacitor is not required for

ISOFT-START = COUT (μF) × 0.06 (V/μs) + ILOAD (mA)

(1)

stability, it is good analog design practice to connect

a 0.1-

μF to 1-μF low ESR capacitor across the VIN

The output voltage ramp rate is independent of COUT

and GND pins of the regulator. This capacitor

and the load current, and has a typical value of

counteracts reactive input sources and improves

0.06 V/

μs.

transient

response,

noise

rejection,

and

ripple

The TLV705 automatically adjusts the soft-start

rejection. A higher-value capacitor may be necessary

current to supply both the load current and the

if large, fast rise-time load transients are anticipated,

current to charge COUT. For example, if ILOAD = 0 mA

or if the device is not located close to the power

upon enabling the LDO, then ISOFT-START = 1 μF ×

source. If source impedance is more than 2

Ω, a

0.06 V/

μs + 0 mA = 60 mA, which is the current that

0.1-

μF input capacitor may be necessary to ensure

charges the output capacitor. However if ILOAD =

stability.

200 mA, then ISOFT-START = 1 μF × 0.06 V/μs +

200 mA = 260 mA, which is the current required for

charging the output capacitor and supplying the load

current.

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