LM3433 datasheet(11/15 Pages) TI1

11 / 15 page

LM3433

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SNVS535B – OCTOBER 2007 – REVISED MARCH 2008

DIM FET SELECTION

Choose a DIM FET with the lowest RDSON for maximum efficieny and low input current draw during the DIM

cycle. The output voltage during DIM will determine the switching frequency. A lower output voltage results in a

lower switching frequency. If the lower frequency during DIM must be bound, choose a FET with a higher RDSON

to force the switching frequency higher during the DIM cycle.

BOOTSTRAP CAPACITORS

The LM3433 uses two bootstrap capacitors and a bypass capacitor on VCC to generate the voltages needed to

drive the external FETs. A 2.2µF ceramic capacitor or larger is recommended between the VCC and LS pins. A

0.47µF is recommended between the HS and BST pins. A 0.1µF is recommended between BST2 and CGND.

SOFT-START CAPACITOR

The LM3433 integrates circuitry that, when used in conjunction with the SS pin, will slow the current ramp on

start-up. The SS pin is used to tailor the soft-start for a specific application. A capacitor value of 0.1µF on the SS

pin will yield a 12mS soft start time. For most applications soft start is not needed.

ENABLE OPERATION

The EN pin of the LM3433 is designed so that it may be controlled using a 1.6V or higher logic signal. If the

enable function is not used, the EN pin may be tied to VIN or left open. This pin is pulled to VIN internally through

a 100k pull up resistor.

PWM DIM OPERATION

The DIM pin of the LM3433 is designed so that it may be controlled using a 1.6V or higher logic signal. The

PWM frequency easily accomodates more than 40kHz dimming and can be much faster if needed. If the PWM

DIM pin is not used, tie it to CGND or leave it open. The DIM pin is tied to CGND internally through a 100k pull

down resistor.

LAYOUT CONSIDERATIONS

The LM3433 is a high performance current driver so attention to layout details is critical to obtain maximum

performance. The most important PCB board design consideration is minimizing the loop comprised by the main

FET, synchronous FET, and their associated decoupling capacitor(s). Place the VCC bypass capacitor as near as

possible to the LM3433. Place the PWM dimming/shunt FET as close to the LED as possible. A ground plane

should be used for power distribution to the power FETs. Use a star ground between the LM3433 circuitry, the

synchronous FET, and the decoupling capacitor(s). The EP contact on the underside of the package must be

connected to VEE. The two lines connecting the sense resistor to CSN and CSP must be routed as a differential

pair directly from the resistor. A Kelvin connection is recommended. It is good practice to route the DIMO/DIMR,

HS/HO, and LO/LS lines as differential pairs. The most important PCB board design consideration is minimizing

the loop comprised by the main FET, synchronous FET, and their associated decoupling capacitor(s). Optimally

this loop should be orthogonal to the ground plane.

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