ADC10061, ADC10062, ADC10064

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SNAS069E – JUNE 1999 – REVISED MARCH 2013

Since the resistance between the two reference inputs can be as low as 400

Ω, the voltage source driving the

reference inputs should have low output impedance. Any noise on either reference input is a potential cause of

conversion errors, so each of these pins must be supplied with a clean, low noise voltage source. Each reference

pin should be bypassed with a 10 µF tantalum and a 0.1 µF ceramic.

THE ANALOG INPUT

The ADC10061, ADC10062, and ADC10064 sample the analog input voltage once every conversion cycle.

When this happens, the input is briefly connected to an impedance approximately equal to 600

Ω in series with 35

pF. Short-duration current spikes can be observed at the analog input during normal operation. These spikes are

normal and do not degrade the converter's performance.

Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy.

Therefore, only signal sources with output impedances less than 500

Ω should be used if rated accuracy is to be

achieved at the minimum sample time (250 ns maximum). If the sampling time is increased, the source

impedance can be larger. If a signal source has a high output impedance, its output should be buffered with an

operational amplifier. The operational amplifier's output should be well-behaved when driving a switched 35

pF/600

Ω load. Any ringing or voltage shifts at the op-amp's output during the sampling period can result in

conversion errors.

Correct conversion results will be obtained for input voltages greater than GND

50 mV. Do not allow the signal source to drive the analog input pin beyond the Absolute Maximum Rating. If an

analog input pin is forced beyond these voltages, the current flowing through the pin should be limited to 5 mA or

less to avoid permanent damage to the IC. The sum of all the overdrive currents into all pins must be less than

the Absolute Maximum Rating for Package Input Current. When the input signal is expected to extend beyond

this limit, an input protection scheme should be used. A simple input protection network using diodes and

resistors is shown in Figure 21. Note the multiple bypass capacitors on the reference and power supply pins. If

conversion time.

Figure 21. Typical Connection

INHERENT SAMPLE-AND-HOLD

Because the ADC10061, ADC10062, and ADC10064 sample the input signal once during each conversion, they

are capable of measuring relatively fast input signals without the help of an external sample-hold. In a non-

sampling successive-approximation A/D converter, regardless of speed, the input signal must be stable to better

than ±1/2 LSB during each conversion cycle or significant errors will result. Consequently, even for many

relatively slow input signals, the signals must be externally sampled and held constant during each conversion if

a SAR with no internal sample-and-hold is used.

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Product Folder Links: ADC10061 ADC10062 ADC10064