ADC12010

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SNAS185B – APRIL 2003 – REVISED MARCH 2013

PD

The PD pin, when high, holds the ADC12010 in a power-down mode to conserve power when the converter is

not being used. The power consumption in this state is 25 mW with a 10 Mhz clock and the output data pins are

undefined in this mode. The data in the pipeline is corrupted while in the power down mode.

The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 30, 31 and 32.

These capacitors loose their charge in the Power Down mode and must be charged by on-chip circuitry before

conversions can be accurate.

DATA OUTPUTS

The ADC12010 has 12 TTL/CMOS compatible Data Output pins. Valid offset binary data is present at these

way to capture a valid output is to latch the data on the falling edge of the conversion clock (pin 10).

Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for

current spikes can cause on-chip noise that can couple into the analog circuitry, degrading dynamic

performance. Adequate power supply bypassing and careful attention to the ground plane will reduce this

properly latch the ADC output data. The result could be an apparent reduction in dynamic performance.

To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by

connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven

input should be connected to each output pin. Additionally, inserting series 100

Ω resistors at the digital outputs,

close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output

currents, which could otherwise result in performance degradation. See Figure 37.

Figure 37. Simple Application Circuit with Single-Ended to Differential Buffer

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