SP705 datasheet(9/17 Pages) EXAR

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FEATURES

The SP705-708/813L series provides four key

functions:

1. A reset output during power-up, power-

down and brownout conditions.

2. An independent watchdog output that goes

LOW if the watchdog input has not been

toggled within 1.6 seconds.

3. A 1.25V threshold detector for power-fail

warning, low battery detection, or monitoring

a power supply other than +5V.

4. An active-LOW manual-reset that allows

RESET to be triggered by a pushbutton switch.

The SP707/708 devices are the same as the

SP705/706 devices except for the active-HIGH

RESET substitution of the watchdog timer. The

SP813L is the same as the SP705 except an

active-HIGH RESET is provided rather than an

active-LOW

RESET.

The

SP705/707/813L

devices generate a reset when the supply

voltage drops below 4.65V. The SP706/708

devices generate a reset below 4.40V.

The SP705-708/813L series is ideally suited

for

applications

automotive

systems,

intelligent instruments, and battery-powered

computers

and

controllers.

The

SP705-

708/813L

series

ideally

applied

environments where monitoring of power

supply to a µP and its related components is

critical.

THEORY OF OPERATION

The

SP705-708/813L

series

microprocessor (µP) supervisory circuit that

monitors the power supplied to digital circuits

such as microprocessors, microcontrollers, or

memory. The series is an ideal solution for

portable, battery-powered equipment that

requires

power

supply

monitoring.

Implementing this series will reduce the

number of components and overall complexity.

The watchdog functions of this product family

will continuously oversee the operational

status of a system. The operational features

and benefits of the SP705-708/813L series are

described in more detail below.

RESET OUTPUT

A microprocessor's reset input starts the µP in

a known state. The SP705-708/813L series

asserts reset during power-up and prevents

code execution errors during power down or

brownout conditions.

On power-up, once VCC reaches 1.1V, RESET is

a guaranteed logic LOW of 0.4V or less. As VCC

rises, RESET stays LOW. When VCC rises above

the reset threshold, an internal timer releases

RESET after 200ms. RESET pulses LOW

whenever VCC dips below the reset threshold,

such as in a brownout condition. When a

brownout condition occurs in the middle of a

previously initiated reset pulse, the pulse

continues for at least another 140ms. On

power down, once VCC falls below the reset

threshold,

RESET

stays

LOW

and

guaranteed to be 0.4V or less until VCC drops

below 1.1V.

The

SP707/708/813L

active-HIGH

RESET

output is simply the complement of the RESET

output and is guaranteed to be valid with VCC

down to 1.1V. Some µPs, such as Intel's

80C51, require an active-HIGH reset pulse.

WATCHDOG TIMER

The

SP705/706/813L

watchdog

circuit

monitors the µP's activity. If the µP does not

toggle the watchdog input (WDI) within 1.6

seconds and WDI is not tri-stated, WDO goes

LOW. As long as RESET is asserted or the WDI

input is tri-stated, the watchdog timer will stay

cleared and will not count. As soon as RESET

is released and WDI is driven HIGH or LOW,

the timer will start counting. Pulses as short as

50ns can be detected.

Typically, WDO will be connected to the non-

maskable interrupt input (NMI) of a µP. When

VCC drops below the reset threshold, WDO will

go LOW whether or not the watchdog timer

had timed out. Normally this would trigger an

NMI but RESET goes LOW simultaneously and

thus overrides the NMI.

If WDI is left unconnected, WDO can be used

as a low-line output. Since floating WDI

disables the internal timer, WDO goes LOW

only when VCC falls below the reset threshold,

thus functioning as a low-line output.

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