ADC10662, ADC10664

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SNAS076E – JUNE 1999 – REVISED MARCH 2013

Table 1. Input Multiplexer Programming ADC10664

Channel

0

0

0

1

1

0

1

1

Table 2. Input Multiplexer Programming ADC10662

Channel

0

1

Mode 2

In Mode 2, also called “RD mode”, the S/H and RD pins are tied together. A conversion is initiated by pulling both

pins low. The A/D converter samples the input voltage and causes the coarse comparators to become active. An

internal timer then terminates the coarse conversion and begins the fine conversion. 470 ns (typical) after S/H

and RD are pulled low, INT goes low, indicating that the conversion is completed. Approximately 20 ns later the

data appearing on the TRI-STATE output pins will be valid. Note that data will appear on these pins throughout

the conversion, but until INT goes low the data at the output pins will be the result of the previous conversion.

REFERENCE CONSIDERATIONS

differential and define the zero to full-scale range of the input signal. The reference inputs can be connected to

required.

1 LSB = 1.953 mV). Note, however, that linearity and offset errors become larger when lower reference voltages

are used. See Typical Performance Characteristics for more information. For this reason, reference voltages less

than 2V are not recommended.

offset from ground. This situation is easily accommodated by the reference configuration used in the ADC10662

connected to a voltage other than ground, bypass it with multiple capacitors.

Since the resistance between the two reference inputs can be as low as 400

Ω, the voltage source driving the

reference inputs should have low output impedance. Any noise on either reference input is a potential cause of

conversion errors, so each of these pins must be supplied with a clean, low noise voltage source. Each reference

pin should be bypassed with a 10

μF tantalum and a 0.1 μF ceramic.

THE ANALOG INPUT

The ADC10662 and ADC10664 sample the analog input voltage once every conversion cycle. When this

happens, the input is briefly connected to an impedance approximately equal to 600

Ω in series with 35 pF. Short-

duration current spikes can be observed at the analog input during normal operation. These spikes are normal

and do not degrade the converter's performance.

Large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy.

Therefore, only signal sources with output impedances less than 500

Ω should be used if rated accuracy is to be

achieved at the minimum sample time (250 ns maximum). If the sampling time is increased, the source

impedance can be larger. If a signal source has a high output impedance, its output should be buffered with an

operational amplifier. The operational amplifier's output should be well-behaved when driving a switched 35

pF/600

Ω load. Any ringing or voltage shifts at the op-amp's output during the sampling period can result in

conversion errors.

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