B13 datasheet(4/14 Pages) MICREL

4 / 14 page

Micrel, Inc.

SM803020

July 22, 2013

Revision 1.0

hbwhelp@micrel.com or (408) 955-1690

Pin Number

Pin Name

Pin Type

Pin Level

Pin Function

B34

B35

VSSOC1

VSSOC2

VSSOC3

PWR

Power Supply Ground for Outputs QC1−3

B39

VSSOD1

VSSOD2

VSSOD3

PWR

Power Supply Ground for Outputs QD1−3

A34

VSSAP1

PWR

Power Supply Ground for PLL1

A22

VSSAP2

PWR

Power Supply Ground for PLL2

A23

VSSI1

PWR

Power Supply Ground for VCXO, Reference1, Feedback 1

A31

VSSI2

PWR

Power Supply Ground for XO, Reference2, Feedback 2

B14

OEA1/2/3

I, (SE)

LVCMOS

Output Enable, Outputs Q0–Q3 disable to tri-state,

0 = Disabled, 1 = Enabled, 75kΩ pull-up

A12

OEB1/2/3

I, (SE)

LVCMOS

Output Enable, Outputs Q4–Q7 disable to tri-state,

0 = Disabled, 1 = Enabled, 75kΩ pull-up

B38

OEC1/2/3

I, (SE)

LVCMOS

Output Enable, Outputs Q4–Q7 disable to tri-state,

0 = Disabled, 1 = Enabled, 75kΩ pull-up

OED1/2/3

I, (SE)

LVCMOS

Output Enable, Outputs Q4–Q7 disable to tri-state,

0 = Disabled, 1 = Enabled, 75kΩ pull-up

A5, A6, A7,

B5, B6, B7

TEST

Factory Test pins. Do not connect anything to these pins.

A32

A33

REFOUT_P,

REFOUT_N

I, (Diff/SE)

LVPECL

LVDS

HCSL

LVCMOS

Reference Clock Output

B21

B22

REF1_P, REF1_N

I, (Diff/SE)

LVPECL

LVDS

HCSL

LVCMOS

Reference Clock Input 1

B28

B29

REF2_P, REF2_N

I, (Diff/SE)

LVPECL

LVDS

HCSL

LVCMOS

Reference Clock Input2

B23

B24

FB1_P, FB1_N

I, (Diff/SE)

LVPECL

LVDS

HCSL

LVCMOS

Feedback Clock Input1

B26

B27

FB2_P, FB2_N

I, (Diff/SE)

LVPECL

LVDS

HCSL

LVCMOS

Feedback Clock Input2

A29

XTAL_IN

I, (SE)

12pF crystal

Crystal Reference Input, no load caps needed

(See Figure 9.)

A30

XTAL_OUT

O, (SE)

12pF crystal

Crystal Reference Output, no load caps needed

(See Figure 9.)

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