TUSB501

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SLLSEG5A – AUGUST 2013 – REVISED AUGUST 2013

DEVICE CONFIGURATION

Table 1. Control Pin Effects (Typical Values)

PIN

DESCRIPTION

LOGIC STATE

GAIN

Low

3 dB

EQ

Equalization Amount

Floating

6 dB

High

9 dB

OUTPUT DIFFERENTIAL VOLTAGE

PIN

DESCRIPTION

LOGIC STATE

FOR THE TRANSITION BIT

Low

Output Swing

OS

Amplitude

High

PIN

DESCRIPTION

LOGIC STATE

FOR OS = LOW

FOR OS = HIGH

Low

0 dB

–2.6 dB

De-Emphasis

DE

Floating

–3.5 dB

–5.9 dB

Amount

High

–6.2 dB

–8.3 dB

(1)

Typical values

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

MIN

MAX

UNIT

–0.5

4

V

Differential I/O

–0.5

4

V

Voltage range at any input or output

terminal

CMOS inputs

–0.5

V

±5

Electrostatic discharge

kV

±1.5

–65

150

°C

-40

105

°C

(1)

Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to the GND terminals.

(3)

Tested in accordance with JEDEC Standard 22, Test Method A114-B.

(4)

Tested in accordance with JEDEC Standard 22, Test Method C101-A.

THERMAL INFORMATION

TUSB501

UNITS

DRF

Junction-to-ambient thermal resistance

102.4

Junction-to-case(top) thermal resistance

90.3

Junction-to-board thermal resistance

21.2

°C/W

Junction-to-top characterization parameter

70

Junction-to-board characterization parameter

3.6

Junction-to-case(bottom) thermal resistance

70.2

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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