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WM1811A Datasheet(PDF) 55 Page - Wolfson Microelectronics plc

Part # WM1811A
Description  Multi-Channel Audio Hub CODEC for Smartphones
PDF  328 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM1811A Datasheet(HTML) 55 Page - Wolfson Microelectronics plc

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Production Data
WM1811A
w
PD, November 2013, Rev 4.1
55
DIGITAL PULL-UP AND PULL-DOWN
The WM1811A provides integrated pull-up and pull-down resistors on the DMICDAT pin. This
provides a flexible capability for interfacing with other devices. Each of the pull-up and pull-down
resistors can be configured independently using the register bits described in Table 12.
Note that, if the DMICDAT digital microphone channels are disabled, or if DMICDAT1_PU and
DMICDAT1_PD are both set, then the pull-up and pull-down will be disabled.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R1824
(0720h)
Pull Control
(1)
9
DMICDAT1_PU
0
DMICDAT Pull-Up enable
0 = Disabled
1 = Enabled
8
DMICDAT1_PD
0
DMICDAT Pull-Down enable
0 = Disabled
1 = Enabled
Table 12 Digital Pull-Up and Pull-Down Control
ANALOGUE TO DIGITAL CONVERTER (ADC)
The WM1811A uses stereo 24-bit sigma-delta ADCs. The use of multi-bit feedback and high
oversampling rates reduces the effects of jitter and high frequency noise. The oversample rate can be
adjusted, if required, to reduce power consumption - see “Clocking and Sample Rates” for details. The
ADC full scale input level is proportional to AVDD1 - see “Electrical Characteristics”. Any input signal
greater than full scale may overload the ADC and cause distortion.
The ADCs are enabled by the ADCL_ENA and ADCR_ENA register bits.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R4 (0004h)
Power
Management (4)
1
ADCL_ENA
0
Left ADC Enable
0 = Disabled
1 = Enabled
0
ADCR_ENA
0
Right ADC Enable
0 = Disabled
1 = Enabled
Table 13 ADC Enable Control
The outputs of the ADCs can be routed to the AIF1 digital audio interface output paths.
Digital volume control of the ADC outputs in the AIF1 signal paths is provided using the registers
described in the “Digital Volume and Filter Control” section.
The outputs of the ADCs can also be routed, in a limited number of configurations, to the digital mixing
output bus, via the digital sidetone signal paths. See “Digital Mixing” for further details.
Digital volume control of the ADC outputs in the digital sidetone signal paths is provided using the
registers described in the “Digital Mixing” section.



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