HD74AC164/HD74ACT164

2

Logic Symbol

A

B

CP

Pin Names

A, B

Data Inputs

CP

Clock Pulse Input (Active Rising Edge)

MR

Master Reset Input (Active Low)

Q

Outputs

Functional Description

The HD74AC164/HD74ACT164 is an edge-triggered 8-bit shift register with serial data entry and an

output from each of the eight stages. Data is entered serially through one of two inputs (A or B); either of

these inputs can be used as an active High Enable for data entry through the other inputs. An unused input

must be tied High.

Each Low-to-High transition on the Clock (CP) input shifts data one place to the right and enters into Q

0

the logical AND of the two data inputs (A•B) that existed before the rising clock edge. A Low level on the

Master Reset (

MR) input overrides all other inputs and clears the register asynchronously, forcing all Q

outputs Low.