13

HV461

Pin

Name

Description

31

SW1

Primary–side P-channel switch driver output.

32

PGND

Power ground. Connect to AGND and DGND close to the IC.

33

VGD

Supply for the SW1–4 drivers. An external boost converter controlled by VDR provides 9.6V for

driving the power stage MOSFETs. An undervoltage condition on this supply pin disables ringer

output and activates the FAULT output.

34

VDR

Gate drive for the external boost converter circuit. Outputs a fixed 50% duty cycle at the ringer

PWM frequency (see ROSC, pin 9). Output voltage regulation is via burp-mode operation. This

output is boostrapped to VGD, thus during startup VDR amplitude is VDD and after startup is

VGD. (See VGD, pin 33)

35

DVDD

Supply for the digital section. 3.0V to 3.6V input. Undervoltage disables ringer output. Must be

from the same source as AVDD. Bypass with a 100nF capacitor to ground as close as possible

to the IC. An undervoltage condition on this supply pin disables ringer output and activates the

FAULT output.

36

CL+

Current limit amplifier non-inverting input.

37

CL-

Current limit amplifier inverting input.

38

CLCOMP

Current limit compensation. An RC network connected between this pin and CL- establishes

current limit reaction time and stability.

39

DIFFAMP+

Differential amplifier non-inverting input. The differential amplifier sets gain, establishing output

amplitude and DC offset in conjunction with AMPx and

OFFx.

Gain = R

see schematic)

40

DIFFAMP-

Differential amplifier inverting input.

41

DIFFAMPO Differential amplifier output.

42

COMP2

Error amplifier compensation. An RC network connected between these pins establishes loop

stability.

43

COMP1

COMP1 is the error amp inverting input. COMP2 is the error amp output.

44

SINEREF

Sine wave reference. Amplitude is 2V

external 33nF capacitor from this pin to ground should be employed to remove high frequency

RING

45

AGND

Analog ground. Connect to AGND and DGND close to the IC.

46

VDCL

Voltage applied to this pin sets the min/max duty cycle limits. If the PWM controller hits these limits, clipping

of the ringer output will occur and the FAULT output will be activated. D

47

DCREF1

In conjunction with the OFFx control inputs, voltages applied to these inputs set the output DC offset. Output

offset is the selected DCREFx voltage multiplied by gain. See also OFF0 & OFF1 (pins 17 & 18)

48

DCREF2