L7986 datasheet(25/43 Pages) STMICROELECTRONICS

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L7986

Application information

In Figure 14 the Bode diagram of the PWM and LC filter transfer function [GPW0 · GLC(f)]

and the open-loop gain [GLOOP(f) = GPW0 · GLC(f) · GTYPEII(f)] are drawn.

Figure 14. Open-loop gain: module Bode diagram

The guidelines for positioning the poles and the zeroes and for calculating the component

values can be summarized as follows:

Choose a value for R1, usually between 1 k and 5 k, in order to have values of C4

and C5 not comparable with parasitic capacitance of the board.

Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means:

Equation 29

where fESR is the ESR zero:

Equation 30

and VS is the sawtooth amplitude. The voltage feed-forward keeps the ratio VS/VIN constant.

Calculate C4 by placing the zero one decade below the output filter double pole:

Equation 31

Then calculate C3 in order to place the second pole at four times the system bandwidth

(BW):

Equation 32

fESR

fLC

------------





fESR

------------

VIN

--------- R1





fESR

 ESR C

OUT



--------------------------------------------

 R

4 fLC



-------------------------------

 R

4 C4 4BW



–



--------------------------------------------------------------

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