HT27LC512 datasheet(6/10 Pages) HOLTEK

6 / 10 page

Functional Description

Operation mode

All the operation modes are shown in the table following.

Mode

OE/VPP

Output

Read

VIL

X (2)

Dout

Output Disable

VIL

VIH

High Z

Standby (TTL)

VIH

High Z

Standby (CMOS)

VCC

± 0.3V

High Z

Program

VIL

VPP

DIN

Program Verify

VIL

DOUT

Product Inhibit

VIH

VPP

High Z

Manufacturer Code (3)

VIL

VH (1)

Device Code (3)

VIL

VIH

VH (1)

Notes: (1) VH = 12.0V

± 0.5V

(2) X=Either VIH or VIL

(3) For Manufacturer Code and Device Code, A1=VIH, When A1=VIL, both codes will read 7F

Programming of the HT27LC512

When the HT27LC512 is delivered, the chip has

all 512K bits in the “ONE”, or HIGH state.

“ZEROs” are loaded into the HT27LC512

through the procedure of programming.

The programming mode is entered when

12.2

±0.2V is applied to the OE/VPP pin and CE

is at VIL. For programming, the data to be

programmed is applied with 8 bits in parallel to

the data pins.

The programming flowchart in Figure 3. shows

the fast interactive programming algorithm.

The interactive algorithm reduces program-

ming time by using 30

µs to 105µs programming

pulses and giving each address only as many

pulses as is necessary in order to reliably pro-

gram the data. After each pulse is applied to a

given address, the data in that address is veri-

fied. If the data is not verified, additional pulses

are given until it is verified or until the maxi-

mum number of pulses is reached. This process

is repeated while sequencing through each ad-

dress of the HT27LC512. This part of the pro-

gramming algorithm is carried at VCC=5.8V to

assure that each EPROM bit is programmed to

a sufficiently high threshold voltage. This en-

sures that all bits have sufficient margin. After

the final address is completed, the entire

EPROM memory is read at VCC=VPP=5.25

±0.25V

to verify the entire memory.

Program inhibit mode

Programming of multiple HT27LC512 in paral-

lel with different data is also easily accom-

plished by using the Program Inhibit Mode.

Except for CE, all like inputs of the parallel

HT27LC512 may be common. A TTL low-level

program pulse applied to an HT27LC512 CE

input with OE/VPP=12.2

±0.2V will program that

HT27LC512. A high-level CE input inhibits the

other HT27LC512 from being programmed.

Program verify mode

Verification should be performed on the pro-

grammed bits to determine whether they were

correctly programmed. The verification should

be performed with OE/VPP and CE at VIL. Data

should be verified at tDV after the falling edge

of CE.

HT27LC512

6th May ’99

HT27LC512 Datasheet(PDF) 6 Page - Holtek Semiconductor Inc

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