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HTG2150 Datasheet(PDF) 13 Page - Holtek Semiconductor Inc |
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HTG2150 Datasheet(HTML) 13 Page - Holtek Semiconductor Inc |
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13 / 49 page ![]() HTG2150 13 July 24, 2000 Preliminary Arithmetic and logic unit - ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data op- eration but also changes the status register. Status register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PD) and watchdog time-out flag (TO). It also records the status information and controls the operation se- quence. With the exception of the TO and PD flags, bits in the status register can be altered by instruc- tions like any other register. Any data written into the status register will not change the TO or PD flags. In addition it should be noted that operations related to the status register may give different results from those intended. The TO and PD flags can only be changed by system power up, Watchdog Timer overflow, executing the HALT instruction and clearing the Watch- dog Timer. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on entering the interrupt sequence or executing the subroutine call, the status reg- ister will not be automatically pushed onto the stack. If the contents of status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. Interrupt The HTG2150 provides an external interrupt and a PWM D/A interrupt and internal timer inter- rupts. The Interrupt Control register (INTC;0BH, INTCH;1EH) contains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may happen during this interval but only the inter- Labels Bits Function C0 C is set if the operation results in a carry during an addition operation or if a bor- row does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. AC 1 AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. Z2 Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. OV 3 OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. PD 4 PD is cleared when either a system powers up or a CLR WDT instruction is exe- cuted. PD is set by executing the HALT instruction. TO 5 TO is cleared by a system power-up or executing the CLR WDT or HALT in- struction. TO is set by a WDT time-out. ¾ 6, 7 Undefined bits, read as ²0². Status register |
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