1-569

Figure 12. Operating Circuit for Burn-In and Steady State

Life Tests. All Channels Tested Simultaneously.

GND

VCC

VO

D.U.T.*

NOTE: BASE LEAD NOT CONNECTED.

TA = +125 °C

VOC

NOMINAL CONDITIONS

PER CHANNEL: IF = 20 mA

VCC

VIN

+–

(EACH OUTPUT)

(EACH INPUT)

IO = 4 mA

ICC = 30 µA

0.1 µF

GND

VCC

D.U.T.

RL

220

Ω

5 V

VCC

LOGIC GATE

0.01 µF

EACH CHANNEL

TTL

Logic Family

LSTTL

CMOS

Device No.

54LS14

CD40106BM

5 V

5 V

15 V

18 k

Ω*

8.2 k

Ω

22 k

Ω

*The equivalent output load resistance is affected by the

LSTTL input current and is approximately 8.2 k

Ω.

This is a worst case design which takes into account 25%

degradation of CTR. See App. Note 1002 to assess actual

degradation and lifetime.

VFF

GND

VCC

IF

VCM

RL

+5 V

VO

+–

PULSE GEN.

NOTE: BASE LEAD NOT CONNECTED.

A

B

D.U.T.

RM

SINGLE CHANNEL OR

COMMON VCC DEVICES

Figure 10. Test Circuit for Transient Immunity and Typical Waveforms.

Figure 11. Recommended Logic Interface.