HDMP-1526 datasheet(3/14 Pages) HP

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parallel data (see Figure 3). This

clock is multiplied by 10 to

generate the 1062.5 MHz clock

necessary for the high-speed

serial outputs.

FRAME MUX

The FRAME MUX accepts the 10-

bit wide parallel data from the

INPUT LATCH. Using internally

generated high-speed clocks, this

parallel data is multiplexed into

the 1062.5 MBd serial data

stream. The data bits are

transmitted sequentially, from the

least significant bit (TX[0]) to the

most significant bit (TX[9]).

OUTPUT SELECT

The OUTPUT SELECT block

provides for an optional internal

loopback of the high-speed serial

signal, for testing purposes.

In normal operation, LOOPEN is

set low and the serial data stream

is placed at

± DOUT. When wrap-

mode is activated by setting

LOOPEN high, the

± DOUT pins

are held static and the serial

output signal is internally

wrapped to the INPUT SELECT

box of the receiver section.

INPUT SELECT

The INPUT SELECT block

determines whether the signal at

± DIN or the internal loop-back

serial signal is used. In normal

operation, LOOPEN is set low

and the serial data is accepted at

± DIN. When LOOPEN is set

high, the high-speed serial signal

is internally looped-back from the

transmitter section to the receiver

section. This feature allows for

loop-back testing exclusive of the

transmission medium.

RX PLL/CLOCK RECOVERY

The RX PLL/CLOCK RECOVERY

block is responsible for frequency

and phase locking onto incoming

serial data stream and recovering

the bit and byte clocks.

In order to accomplish this, upon

startup, the user should set

-LCKREF low for a period of at

least 500

µsec. This allows the

PLL to first frequency lock onto

the 106.25 MHz reference clock

provided at the REFCLK input.

The RX PLL/CLOCK RECOVERY

circuitry multiplies this reference

clock by 10 to generate an

internal 1062.5 MHz clock. After

500

µsec, the user should set

-LCKREF high. This will allow the

receiver to frequency and phase

lock the internal 1062.5 MHz

clock onto the incoming serial

data stream. Once locked, the

receiver will recover the two

53.125 MHz receiver byte clocks

(RBC1/RBC0). These byte clocks

are approximately 180

° out of

phase with each other and are

alternately used to clock the

10-bit parallel output data.

INPUT SAMPLER

The INPUT SAMPLER is

responsible for converting the

serial input signal into a retimed

serial bit stream. In order to

accomplish this, it uses the high

speed serial clock recovered from

the RX PLL/CLOCK RECOVERY

block. This serial bit stream is

sent to the FRAME DEMUX and

BYTE SYNC block.

FRAME DEMUX AND BYTE

SYNC

The FRAME DEMUX AND BYTE

SYNC block is responsible for

restoring the 10-bit parallel data

from the high speed serial bit

stream. This block is also

responsible for recognizing the

comma character (or a K28.5

character) of positive disparity

(0011111xxx). When recognized,

the FRAME DEMUX AND BYTE

SYNC block works with the RX

PLL/CLOCK RECOVERY block to

properly align the receive byte

clocks to the parallel data. When

a comma character is detected

and realignment of the receiver

byte clocks (RBC1/RBC0) is

necessary, these clocks are

stretched, not slivered, to the

next possible correct alignment

position. These clocks will be

fully aligned by the start of the

second 4-byte ordered set. The

second comma character received

shall be aligned with the rising

edge of RBC1. Comma characters

should not be transmitted in

consecutive succession to allow

the receiver byte clocks to

maintain their proper recovered

frequencies.

OUTPUT DRIVERS

The OUTPUT DRIVERS present

the 10-bit parallel recovered data

byte properly aligned to the

receive byte clocks (RBC1/

RBC0), as shown in Figure 4.

These output data buffers provide

TTL compatible signals.

HDMP-1526 Datasheet(PDF) 3 Page - Agilent(Hewlett-Packard)

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