6

AT24C01A/02/04/08A/16A

5092D–SEEPR–4/07

MEMORY RESET: After an interruption in protocol, power loss or system reset, any

two-wire part can be reset by following these steps:

1.

Clock up to 9 cycles.

2.

Look for SDA high in each cycle while SCL is high.

3.

Create a start condition.

Bus Timing

Figure 2. SCL: Serial Clock, SDA: Serial Data I/O

Write Cycle Timing

Figure 3. SCL: Serial Clock, SDA: Serial Data I/O

Note:

1. The write cycle time t

twr

(1)

STOP

CONDITION

START

CONDITION

WORDn

ACK

8th BIT

SCL

SDA