HC2510C

3

Table 1. Pin Description

Pin Name

Pin No.

Type

Functional Description

CLK

24

I

Clock Input. CLK provides the reference signal to the internal

PLL.

FBIN

13

I

Feedback Input. FBIN provides the feedback signal to the

internal PLL.

G

11

I

Output Bank Enable. When G is high, all outputs 1Y(0:9) are

enabled.

When G is low, Outputs 1Y(0:9) are disable to a logic-low

state.

FBOUT

12

O

Feedback Output. FBOUT completes the feedback loop of the

PLL by being wired to FBIN.

1Y(0:9)

3,4,5,8,9

15,16,17,20,2

1

O

Clock Outputs. These outputs provide low-skew copies of

CLKIN. Each output has an embedded series-damping

resistor.

23

Power

bypassed and CLK is buffered directly to the device outputs.

AGND

1

Groun

d

Analog Ground. AGND provides the ground reference for the

analog circuitry.

2,10,14,22

Power

Power Supply

GND

6,7,18,19

Groun

d

Ground

Table 2. Absolute Maximum Ratings Over Operating Free-air

Temperature Range

Symbols

Parameter

Value

Unit

Conditions

Supply Voltage Range

-0.5 to 4.6

V

Input Voltage Range

-0.5 to 6.5

V

Voltage Range applied to any

input in the high or low state

-0.5 to Vcc+0.5

V

Input Clamp Current

±50

mA

Output Clamp Current

±50

mA

Continuous Output Current

±50

mA

Maximum Power Dissipaiton

0.7

W

Storage Temperature Range

- 65 to 150

°C