GMS87C4060 datasheet(77/100 Pages) HYNIX

77 / 100 page

HMS81C43xx / GMS87C4060

November 2001 ver 1.2

20. WATCHDOG TIMER

The watchdog timer rapidly detects the CPU malfunction

such as endless looping caused by noise or the like, and re-

sumes the CPU to the normal state.

The watchdog timer signal for detecting malfunction can

be selected either a reset CPU or a interrupt request.

When the watchdog timer is not being used for malfunc-

tion detection, it can be used as a timer to generate an in-

terrupt at fixed intervals.

Figure 20-1 Block Diagram of Watchdog Timer

Watchdog Timer Control

Figure 20-2 shows the watchdog timer control register.

The watchdog timer is automatically disabled after reset.

The CPU malfunction is detected as setting the detection

time, selecting output, and clearing the binary counter. Re-

peatedly clearing the binary counter within the setting de-

tection time.

If the malfunction occurs for any cause, the watchdog tim-

er output will become active at the rising overflow from

the binary counters unless the binary counter are cleared.

At this time, when WDTON=1 a reset is generated, which

drives the RESET pin low to reset the internal hardware.

When WDTON=0, a watchdog timer interrupt (IFWDT) is

generated.

Figure 20-2 Watchdog timer register

to reset CPU

WDTR

Watchdog Timer Register

(BIT overflow : IFBIT)

Clock source

6-bit up-counter

enable

WDT

6-bit compare data

comparator

WDTR[bit5~0]

Watchdog Timer interrupt

WDTCL[bit6]

clear

[00D7H]

IFWDT

CKCTLR

Clock control Register

[00D6H]

WDTON[bit5]

CKTCLR

ADDRESS : 00D6H

RESET VALUE : 0000 0000b

WDT

ENP

BTCL BTS2

BTS1

BTS0

Watchdog timer On/Off control

WWWR

WDTR

ADDRESS : 00D7H

RESET VALUE : -011 1111b

WDT

W D TR 5

Slave address

WWWWWW

0: Normal 6bit timer, Watchdog off

1: Watchdog timer

Watchdog timer Clear

0: Watchdog timer free run

1: Watchdog timer clear and free run

Automatically cleared this bit after 1cycle

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