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AV9172-03CC16 Datasheet(PDF) 6 Page - Integrated Circuit Systems

Part # AV9172-03CC16
Description  Low Skew Output Buffer
PDF  8 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

AV9172-03CC16 Datasheet(HTML) 6 Page - Integrated Circuit Systems

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AV9172
Electrical Characteristics
VDD =+5V±5%, TA=0°C to 70°C unless otherwise stated
*Parameter guaranteed by design and characterization. Not 100% tested in production.
Notes:
1. Output frequency includes both the Fast Clock (2X or 1X) and the Slow Clock (1X or 0.5X) extremes.
2. All skew specifications are measured with a 50W transmission line, load terminated with 50W to 1.4V.
3. Duty cycle measured at 1.4V.
4. Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
DC Characteristics
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Input Low Voltage
VIL
VDD=5V
-
-
0.8
V
Input High Voltage
VIH
VDD=5V
2.0
-
-
V
Input Low Current
IIL
VIN=0V
-5
-
5
µA
Input High Current
IIH
VIN=V
-5
-
5
µA
Output Low Voltage
VOL*IOL=25mA
-
0.5
0.8
V
Output High Voltage
VOH*IOH=-25mA
2.4
-
-
V
Supply Current
IDD
Unloaded, 50 MHz outputs
-
35
60
mA
AC Characteristics
Input Clock Rise Time
ICLKr*-
-
10
ns
Input Clock Fall Time
ICLKf*-
-
10
ns
Output Rise time, 0.8 to 2.0V
tr*
15pF load
-
0.7
1
ns
Rise time, 20% to 80% VDD
tr*
15pF load
-
1.2
2
ns
Output Fall time, 2.0 to 0.8V
tf*
15pF load
-
0.7
1
ns
Fall time, 80% to 20% VDD
tf*
15pF load
-
1.2
2
ns
Output Duty cycle
dt*
15pF load
45
49/51
55
%
Jitter, 1 sigma
T1s*60
ps
Jitter, absolute
Tabs*
ae200
ps
Input Frequency (-01,-03)
fi*
10
50
MHz
Input Frequency (-07)
fi*
20
100
MHz
Output Frequency
(-01,-03, -07)
fo*
Note 1
10
100
MHz
FBIN to IN skew
tskew1*
Note 2, 4. Input rise time
< 3ns
-500
-300
500
ps
FBIN to IN skew
tskew1*
Note 2, 4. Input rise time
< 10ns
1000
-500
1000
ps
Skew between any 2 outputs at
same frequency
tskew2*
Note 2, 4
-250
±50
250
ps
Skew between any 2 outputs at
different frequencies
Note 2, 4
500
ps



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