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ICS580-01 Datasheet(PDF) 4 Page - Integrated Circuit Systems

Part # ICS580-01
Description  Glitch-Free Clock Multiplexer
PDF  6 Pages
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Manufacturer  ICST [Integrated Circuit Systems]
Direct Link  http://www.icst.com
Logo ICST - Integrated Circuit Systems

ICS580-01 Datasheet(HTML) 4 Page - Integrated Circuit Systems

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ICS580-01
Glitch-Free Clock Multiplexer
MDS 580-01 A
4
Revision 030300
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
In the third example, the ICS580-01 is configured to automatically switch clocks when an an input stops.
The clock that could stop is connected to INA while the backup, always running, clock is connected to INB.
The output NO_INA is connected to SELB. This means that when the clock on INA stops, NO_INA
goes high selecting the clock on INB which is muxed to the output after 3 cycles. When the clock on
INA restarts, NO_INA immediately goes low, selecting the clock on INA. The output then switches in
the manner described in the first example.
SELB
DIV
VDDI
INA
INB
GND
OE4
OE3
OE1
VDDC
CLK1
CLK2
GND
OE2
NO_INA
VDD
0.01µF
33
Ω
0.01µF
Normal
Clock
Backup
Clock
NO_INB
Output
Clock
Figure 3
The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and
NO_INB are unused and so are disabled by grounding OE2 and OE4. A 33
Ω series termination resistor
is used on the clock output and 2 decoupling capacitors of 0.01µF are used. All other inputs are left
floating and are therefore pulled high by the on-chip pull-ups.
Output Enable
Each output has a dedicated output enable pin. If an output is unused, it should be tri-stated by tying the
appropriate output enable pin to ground.
External Components
The ICS580-01 requires two 0.01µF decoupling capacitors, one between VDDI and GND and one between
VDDC and GND. Series termination resistors of 33
Ω can be used on CLK1 and CLK2.
Split Power Supplies
The VDDI pin provides the power for the INA and INB input buffers only. All the other inputs and the
rest of the chip are connected to VDDC. This allows for supply voltage translation. For example, INA and
INB could be 5 V clocks (VDDI=5 V) and the rest of the chip could use a 3.3 V supply on VDDC giving
3.3 V output clocks. For correct operation VDDI must always be greater than or equal to VDDC.



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