ICS671-01

Zero Delay, Low Skew Buffer and Multipler

MDS 671-01 B

2

Revision 051700

Printed 11/15/00

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com

Pin Descriptions

Key: I = Input; O = output; P = power supply connection.

Pin Assignment

ICS671-01

External Components

The ICS671-01 requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.01µF should be connected between VDD and GND on pins 4 and 5, and VDD and GND

on pins 13 and 12, as close to the device as possible. A series termination resistor of 33

Ω may be used close

to each clock output pin to reduce reflections.

16

15

14

13

16 pin narrow (150 mil) SOIC

12

11

10

9

1

2

3

4

5

6

7

8

CLK1

GND

FBIN

CLKIN

VDD

S0

CLK3

CLK4

VDD

GND

CLK5

S1

CLK6

CLK8

CLK7

CLK2

Number

Name

Type

Description

1

CLKIN

I

Clock Input.

2, 3, 6, 7,

10, 11

CLK1:6

O

Clock Outputs 1:6. See above table.

4, 13

VDD

P

Power supply. Connect both pins to same voltage (either 3.3 V or 5 V).

5, 12

GND

P

Connect to ground.

8

S0

I

Select input 0. See table above.

9

S1

I

Select input 1. See table above.

14

CLK7

I

Clock Output 7. See table above.

15

CLK8

I

Clock Output 8. See table above. Normally use this clock as feedback.

16

FBIN

I

Feedback Input. Connect to CLK8 under normal operations.

S1

S0

CLK1:6

CLK7

CLK8

Input range

0

0

Tri-state (high impedance)

Tri-state (high impedance)

Tri-state (high impedance)

-

0

1

x2

x5

x1

5 to 30 MHz

1

0

x2

x2

x2

15 to 80 MHz

1

1

x4

x4

x4

7.5 to 40 MHz

Output Clock Mode Select Table