Integrated

Circuit

Systems, Inc.

General Description

Features

ICS9112-17

Block Diagram

Low Skew Output Buffer

9112-17 Rev G 10/20/00

Pin Configuration

•

Zero input - output delay

•

Frequency range 25 - 133 MHz (3.3V)

•

High loop filter bandwidth ideal for Spread Spectrum

applications.

•

Less than 200 ps cycle to cycle Jitter

•

Skew controlled outputs

•

Skew less than 250 ps between outputs

•

Available in 16 pin, 150 mil SSOP & SOIC package

The ICS9112-17 is a high performance, low skew, low jitter

zero delay buffer. It uses a phase lock loop (PLL) technology

to align, in both phase and frequency, the REF input with the

CLKOUT signal.

It is designed to distribute high speed

clocks in PC systems operating at speeds from 25 to

133 MHz.

ICS9112-17 is a zero delay buffer that provides

synchronization between the input and output. The

synchronization is established via CLKOUT feed back to the

input of the PLL. Since the skew between the input and

output is less than +/- 350 pS, the part acts as a zero delay

buffer.

The ICS9112-17 has two banks of four outputs controlled by

two address lines. Depending on the selected address line,

bank B or both banks can be put in a tri-state mode. In this

mode, the PLL is still running and only the output buffers are

put in a high impedance mode. The test mode shuts off the

PLL and connects the input directly to the output buffers (see

table below for functionality).

The ICS9112-17 comes in a sixteen pin 150 mil SOIC or 16

pin SSOP package. In the absence of REF input, will be in the

power down mode. In this mode, the PLL is turned off and the

output buffers are pulled low. Power down mode provides

the lowest power consumption for a standby condition.

2

S

F1

S

F

A

K

L

C

)

4

,

1

(

B

K

L

C

)

4

,

1

(

T

U

O

K

L

C

t

u

p

t

u

O

e

c

r

u

o

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L

L

P

n

w

o

d

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u

h

S

00

e

t

a

t

s

i

r

Te

t

a

t

s

i

r

Tn

e

v

i

r

DL

L

PN

01

n

e

v

i

r

De

t

a

t

s

i

r

Tn

e

v

i

r

DL

L

PN

10

L

L

P

s

s

a

p

y

B

e

d

o

M

L

L

P

s

s

a

p

y

B

e

d

o

M

L

L

P

s

s

a

p

y

B

e

d

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F

E

RY

11

n

e

v

i

r

Dn

e

v

i

r

Dn

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v

i

r

DL

L

PN

Functionality

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any

information being relied upon by the customer is current and accurate.

16 pin SSOP & SOIC