2

ICS9148-03

Pin Descriptions

Notes:

1:

Internal Pull-up Resistor of 240K to 3.3V on indicated inputs

2:

Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor

to program logic high to VDD logic low to GND.

3. Internal Pulldown Resistor of 240K to GND on SS_type

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

VDD1

PWR

Ref (0:1), XTAL power supply, nominal 3.3V

2

REF0

OUT

14.318 MHz reference clock.

CPU3.3#_2.5

1,2

IN

Indicates whether VDDL2 is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V

CPU. Latched Input.

3,9,16,22,27,

33,39,45

GND

PWR

Ground

4X1

IN

Crystal input, has internal load cap (33pF) and feedback

resistor from X2

5

X2

OUT

Crystal output, nominally 14.318MHz. Has internal load cap (33pF)

6,14

VDD2

PWR

Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V

7

PCICLK_F

OUT

Free running PCI clock

FS1

1,2

IN

Frequency select pin. Latched Input.

8

PCICLK0

OUT

PCI clock output.

FS2

1,2

IN

Frequency select pin. Latched Input.

10, 11, 12, 13

PCICLK(1:4)

OUT

PCI clock outputs.

15

PCICLK5

OUT

PCI clock output. (In desktop mode, MODE=1)

PCI_STOP#

1

IN

Halts PCICLK (0:5) clocks at logic 0 level, when input low

(In mobile mode, MODE=0)

17, 18, 20, 21,

28, 29, 31, 32,

34, 35,37,38

SDRAM (0:11)

OUT

SDRAM clock outputs.

19,30,36

VDD3

PWR

Supply for SDRAM (0:11), PLL core and 24, 48MHz clocks, nominal

3.3.V

23

SS_EN#

1

IN

Spread Spectrum Enable. Low =Enable

24

SS_TYPE

3

IN

HIGH = Spread Spectrum down spread. LOW = Spread Spectrum Center

spread. Input has Pulldown to GND

25

24MHz

OUT

24MHz output clock

IN

Pin 15, pin 46 function select pin, 1=Desktop Mode, 0=Mobile mode.

Latched Input.

26

48MHz

OUT

48MHz output clock

FS0

1,2

IN

Frequency select pin. Latched Input.

40, 41, 43, 44

CPUCLK(0:3)

OUT

CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low

42

VDDL2

PWR

Supply for CPU (0:3), either 2.5V or 3.3V nominal

46

REF1

OUT

14.318 Mhz reference clock.(in Desktop Mode, MODE=1) This REF Output

is the STRONGER buffer for ISA loads.

CPU_STOP#

1

IN

Halts CPUCLK (0:3) clocks at logic 0 level when input low

(in Mobile Mode, MODE=0)

47

IOAPIC

OUT

IOAPIC clock output. 14.318 MHz Powered by VDDL1.

48

VDDL1

PWR

Supply for IOAPIC, either 2.5V or 3.3V nominal