ICS9169CF-41 datasheet(6/7 Pages) ICST

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ICS9169C-41

Technical Pin Function Descriptions

VDD

This is the power supply to the internal logic of the device as

well as the following clock output buffers:

This pin may be operated at any voltage between 3.0 and 3.7

volts. Clocks from the listed buffers that it supplies will

have a voltage swing from ground to this level. For the

actual guaranteed high and low voltage levels of these clocks,

please consult the AC parameter table in this data sheet.

GND

This is the power supply ground return pin.

This pin serves one of two functions. When the device is

used with a crystal, X1 acts as the input pin for the reference

signal that comes from the discrete crystal. When the device

is driven by an external clock signal, X1 is the device input

pin for that reference clock. This pin also implements an

internal crystal loading capacitor that is connected to ground.

See the data tables for the value of the capacitor.

This pin is used only when the device uses a Crystal as the

reference frequency source. In this mode of operation, X2 is

an output signal that drives (or excites) the discrete crystal.

This pin also implements an internal crystal loading capacitor

that is connected to ground. See the data tables for the value

of the capacitor.

CPU (1:12)

These pins are the clock output that drive the processor and

other CPU related circuitry that require clocks which are in

tight skew tolerance with the CPU clock. See the

Functionality table at the beginning of this data sheet for a

list of the specific frequencies that these clocks operate at

and the selection codes that are necessary to produce these

frequencies. Some of these pin serve dual functions.

PCICLK

Clock output driver for the PCI Bus.

FS0, FS1, FS2

These pins control the frequency of the clocks at the CPU,

BUS and SDRAM pins. See the Funtionality table at the

beginning of this data sheet for a list of the specific

frequencies that these clock operate at and the selection

codes that are necessary to produce these frequencies. The

device reads these pins at power-up and stores the

programmed selection code in an internal data latch. If a "1"

value is desired for a specific frequency selection bit,a 10K

ohm resistor must be connected from the appropriate FS pin

to the VDD supply. If a "O" value is desired, then the 10K

resistor must be connected to ground. After the internal

power On reset latches the input data, these pins become

output clocks and no further frequency selection is possible.

48MHz

This is a fixed frequency clock that is typically used to drive

USB peripheral device needs.

24MHz

This is a fixed frequency clock that is typically used to drive

super I/O peripheral device needs.

REF (0:1)

This is a fixed frequency clock that runs at the same frequency

as the input freerence clock (typically 14.31818 MHz) is

and typically used to drive Video and ISA BUS requirements.

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