2

ICS9248-135

Third party brands and names are the property of their respective owners.

The ICS9248-135 is the single chip clock solution for Desktop/Notebook designs using the SIS 540/630 style chipset. It

provides all necessary clock signals for such a system.

Spread spectrum may be enabled through I

10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-135

employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature

variations.

Serial programming I

General Description

Pin Configuration

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1, 6, 15, 19, 27,

30, 36, 42

VDD

PWR

3.3V Power supply for SDRAM output buffers, PCI output buffers, reference

output buffers and 48MHz output

REF0

OUT

14.318 MHz reference clock.

FS3

IN

Frequency select pin.

3, 10, 16, 22, 33,

39, 44

GND

PWR

Ground pin for 3V outputs.

4

X1

IN

Crystal input,nominally 14.318MHz.

5

X2

OUT

Crystal output, nominally 14.318MHz.

FS1

IN

Frequency select pin.

PCICLK_F

OUT

Free running PCICLK clock output. Not affected by PCI_STOP#

FS2

IN

Frequency select pin.

PCICLK1

OUT

PCI clock outputs.

14, 13, 12, 11, 9

PCICLK (6:2)

OUT

PCI clock outputs.

17

SDRAM_STOP#

IN

Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low

18

PD#

IN

Asynchronous active low input pin used to power down the device into a low

power state. The internal clocks are disabled and the VCO and the crystal are

stopped. The latency of the power down will not be greater than 3ms.

20

CPU_STOP#

IN

Stops all CPUCLKs clocks at logic 0 level, when input low

21

PCI_STOP#

IN

Stops all PCICLKs clocks at logic 0 level, when input low

38, 37, 35, 34,

32, 31, 29, 28

SDRAM (7:0)

OUT

SDRAM clock outputs

23

SDATA

IN

Data input for I

24

SCLK

IN

Clock input of I

CPU2.5_3.3#

IN

Voltage select 2.5V when high - 3.3V when low

24_48MHz

OUT

Clock output for super I/O/USB default is 24MHz

FS0

IN

Frequency select pin.

48MHz

OUT

48MHz output clock

41, 40

SDRAM_F (1:0)

OUT

Free running SDRAM clock outputs. Not affected by SDRAM_STOP#

45, 43

CPUCLK (1:2)

OUT

CPU clock outputs.

46

CPUCLK_F

OUT

Free running CPUCLK clock output. Not affected by CPU_STOP#

47

VDDLCPU

PWR

Power pin for the CPUCLKs. 2.5V

48

REF1

OUT

14.318 MHz reference clock.

26

2

7

8

25