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ICS9248-157

Advance Information

Third party brands and names are the property of their respective owners.

Pin Descriptions

General Description

The ICS9248-157 is the Main clock solution for Notebook designs using the Intel ALI1621/1632M style chipset. Along with

an SDRAM buffer such as the ICS9179-03, it provides all necessary clock signals for such a system.

Spread spectrum may be enabled by driving pin 26, SPREAD# active (Low) at power-on. Spread spectrum typically reduces

system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding.

The ICS9248-157 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process

and temperature variations.

Pin number

Pin name

Type

Description

FS1

Input

Frequency select pin

REF0

Output

3.3V, 14.318 MHz reference clock output.

2

X1

Input

14.318 MHz crystal input

3

X2

Output

14.318 MHz crystal output

FS2

Input

Frequency select pin

PCICLK_F

Output

3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#

SEL_CPUF#

Input

Active low input to select CPUCLK0/F (pin 23) either normal CPUCLK or Free

running (not stoppable through CPU_STOP#) clock.

PCICLK0

Output

3.3V PCI clock output

11, 10, 9, 6

PCICLK (4:1)

Output

3.3 V PCI clock outputs, generating timing requirements

7, 15, 21

GND

Power

Ground for clock outputs

8

VDDPCI

Power

3.3 V power for the PCI clock outputs

12

PCICLK_E

Output

Early PCICLK output, offset from other PCICLKs, stopped by PCI-STOP#

13

VDD48

Power

3.3 V power for 48 MHz clocks

FS3

Input

Frequency select pin

48MHz

Output

Fixed 48MHz clock.

16

DIV4#

Input

Active low input, enables the CPUCLK and the PCICLK to run at 1/4 of the regular

frequecies

17

PD#

Input

Asynchronous active low input pin used to power down the device into a low power

state. The internal clocks are disabled and the VCO and the crystal are stopped. The

latency of the power down will not be greater than 3ms.

18

CPU_STOP#

Input

Asynchronous active low input pin used to stop the CPUCLK in active low state, all

other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at

least 3 CPU clocks.

19

VDDA

Power

3.3 V power for the core

20

PCI-STOP#

Input

Synchronous active low input used to stop the PCICLK in active low state. It will not

effect PCICLK_F or any other outputs.

22

GNDL

Power

Ground for the CPU and Host clock outputs

23

CPUCLK0/F

Output

2.5V CPU clock output; can be selected to be free running by driving

SEL_CPUF# low

24

CPUCLK1

0utput

2.5 V CPU and Host clock outputs

25

VDDL

Power

2.5 V power for the CPU and Host clock outputs

26

SPREAD#

Input

power-on spread spectrum enable option. Active low = spread spectrum clocking

enable. Active high = spread spectrum clocking disable.

FS0

Input

Frequency select pin

REF1

Output

3.3V, 14.318 MHz reference clock output.

28

VDDR

Power

3.3 V power for the REFCLK and crystal clock outputs

14

1

27

4

5